Wiring method of FPGA prototype verification system

Abstract

The invention discloses a wiring method of an FPGA prototype verification system. The wiring method comprises the following steps: converting a wiring diagram of the FPGA prototype system into an undirected connected diagram; taking the short total length of the network and the small number of times of repeated use of edges as targets, and performing wiring on the network based on an approximation algorithm of a minimum Steiner tree; according to the wiring condition and the constraint condition of the network, listing a mathematical plan, and pre-allocating a time division multiplexing ratio; accurately distributing the time division multiplexing ratio, and carrying out further tuning. According to the method, the FPGA prototype system can be successfully wired, and the group with the largest negative effect in all the groups is minimized, so that the system delay is greatly reduced, and the performance of the whole FPGA system is improved.

Description

technical field [0001] The invention belongs to the field of electronic design automation, and in particular relates to a wiring method for an FPGA prototype verification system. Background technique [0002] As the VLSI process becomes more and more advanced, if some loopholes are found in actual manufacturing, the cost of correcting the design and remanufacturing is huge, so it is very necessary to verify at each stage of the VLSI design process , and the cost and time required for verification occupies half of the chip design. [0003] Currently, there are three methods for performing chip logic verification, namely software simulation, processor-based hardware simulation accelerated software simulation, and FPGA prototype verification system. Among them, the verification method based on FPGA prototype has high execution speed, low cost and rich testing experience, so it has high application value. However, the capacity of a single FPGA is limited, so a Multi-FPGA proto...

AI Technical Summary

Problems solved by technology

[0005] Although TDM technology increases the number of signal transmissions between FPGAs, it also has negative effects, the most important of which is the increase in signal delay

This type of delay accounts for a large proportion of the delay of the entire FPGA verification system, resulting in increased delay on the critical path, which in turn leads to performance degradation of the entire FPGA prototype system

Images