Design Method for Optimizing the Metal Routing of Fishbone Clock Tree

Abstract

The invention discloses a design method for optimizing the metal wiring of a herringbone clock tree, which comprises the following steps: 1) before placing the logic units in the chip, the overall module is divided into squares with a side length of 30 microns, and each In a square, the density of logic units is placed so that the logic units are evenly distributed. 2) Take out the vertical coordinates of adjacent fishbone tree branches, calculate the distance between adjacent fishbone tree branches, and record it as a, and create a horizontal line block at the center point of each adjacent branch. 3) Starting from the main trunk of the fishbone tree and taking a as the interval, create vertical routing blockages to the left and right respectively. 4) Grab the line names of the drive of the fishbone clock tree connected to its load, give priority to metal routing for these connections, delete the metal routing obstructions after the routing is completed, and then perform global routing. The invention saves interconnection line resources, optimizes clock structure and improves clock quality.

Description

technical field [0001] The invention designs a design method for optimizing metal wiring of a fishbone clock tree. Background technique [0002] Due to the complexity of the clock structure, when the tool automatically grows the clock tree, in order to balance the clock tree so that the clock signal starts from the same clock source and has the same delay to the clock end of each register, a buffer is usually added to the shorter path. At the same time, the short path is detoured far away, so that the clock delays of the short path and the longer path are balanced to be consistent. With the advancement of technology and the continuous shrinking of feature size, the interconnection delay has become the main delay unit on the timing path. Therefore, this way of winding the far metal line and inserting the buffer of the balance unit virtually increases the winding distance, making the clock signal The propagation delay is greatly increased, resulting in increased power consump...

AI Technical Summary

Problems solved by technology

This is contrary to the original intention of the design, and will cause the main load to be too large, resulting in a large clock conversion time delay, thereby affecting the clock quality, so it is necessary to avoid the situation that the load and the main body have metal connections

Images