An analog-to-digital converter and an analog-to-digital conversion method

Abstract

The embodiment of the present invention discloses an analog-to-digital converter and an analog-to-digital conversion method. The analog-to-digital converter includes: a clock generator, including M transmission gates, and the M transmission gates are used to receive a periodic first clock signal, and perform gating control on the first clock signal respectively to generate M second clock signals, where M is an integer greater than or equal to 2, and each cycle of the first clock signal includes M clock pulses , the period of the M second clock signals is equal to the period of the first clock signal, and each period of the M second clock signals respectively includes one clock pulse in the M clock pulses; M ADC channels configured in a time-interleaved manner are used to receive an analog signal, and respectively perform sampling and analog-to-digital conversion on the analog signal under the control of the M second clock signals to obtain M digital signals , wherein each ADC channel corresponds to one of the M second clock signals; the adder is configured to add the M digital signals in the digital domain to obtain a digital output signal.

Description

technical field [0001] The invention relates to the field of electronic technology, in particular to an analog-to-digital converter and an analog-to-digital conversion method. Background technique [0002] At present, with the rapid development of technologies such as computers, communications and multimedia, the degree of digitalization in high-tech fields is continuously deepening. In the front end and back end of advanced electronic systems, analog-digital converters (analog-digital converters, ADCs) are required, especially in radar, sonar, high-speed and high-resolution video and image displays, medical imaging, high-performance controllers In applications such as transmitters and transmitters and modern digital communications including various radio receivers, the performance requirements of high-speed, high-precision ADCs are getting higher and higher. [0003] In order to take into account the high-speed performance, the current high-precision ADC often adopts the m...

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Problems solved by technology

[0003] In order to take into account the high-speed performance, the current high-precision ADC often adopts the method of timing interleaving, and multiple high-precision ADCs are operated in parallel to form a multi-channel ADC. For multiple clock signals corresponding to the multi-channel ADC, in the traditional technical solution In this method, the corresponding multiple clock signals are uniformly generated by a clock generator including multiple series-connected D flip-flops. In this traditional scheme, since each clock signal has passed through different D flip-flops and output drives, when When there is a process deviation between multiple D flip-flops, the clock skew (time skew) of each clock generally reaches the picosecond (Picosecond, ps) level. Due to the clock skew, it will cause different ADC channels to pass the analog-to-digital conversion Harmonics related to the clock frequency appear on the obtained frequency spectrum, thereby affecting the conversion accuracy of the multi-channel ADC. In order to overcome this problem, the prior art adopts such as figure 1 shown in the approach, figure 1 It includes two AND gates set in parallel, which are respectively used to receive an input clock signal, and a homologous clock signal is used to retime the two input clock signals received by the two AND gates respectively, and the two AND gates respectively perform The falling edges of the two output clock signals obtained after the AND operation are determined by the falling edges of the homologous clock signals. After retiming, the clock offset between the two output clock signals can reach hundreds of femtoseconds ( Femtosecond, fs), however, in the high-speed high-precision interleaved ADC sampling, with the increase of the input signal frequency, the clock offset of hundreds of femtoseconds is difficult to meet the linearity requirements, so it is urgent to design the clock offset shift lower clock generator

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