Circuit for accurately correcting duty ratio of clock signal

Abstract

The invention discloses a circuit for accurately correcting the duty ratio of a clock signal. The circuit comprises an inverter chain, a delay unit, a phase detection unit and a low-pass filter. The inverter chain adopts one CMOS inverter or adopts a plurality of cascaded CMOS inverters. An input signal enters the input end of the inverter chain. The duty ratio of the input signal is adjusted through the change of the grid bias voltage of the first CMOS inverter in the inverter chain, and the inverter chain outputs an output signal subjected to duty ratio correction. And the output signal passes through the time delay unit to obtain a time delay signal. The output signal and the delay signal are used as input of the phase detection unit together, and the phase detection unit outputs an indication signal representing whether the duty ratio of the output signal reaches a target value or not. After high-frequency components of the indication signals are filtered out through a low-pass filter, the remaining low-frequency and direct-current components serve as grid direct-current bias voltage of a first CMOS inverter in the inverter chain. The duty ratio of the output signal can be accurately controlled.

Description

technical field [0001] The present application relates to a circuit for correcting the duty cycle, in particular to a circuit for correcting the duty cycle of a clock signal. Background technique [0002] In modern circuit systems, the clock signal is the most commonly used signal, which can be generated by a crystal oscillator or a ring oscillator. Different circuit modules have different requirements on the clock signal. For example, the analog-to-digital converter requires the edge jitter of the input clock signal to be particularly small; the real-time clock circuit (RTC) requires the frequency of the input clock signal to be very stable; the mixer (Mixer) in some radio frequency circuits requires the local oscillator (LO ) The clock signal generated has a duty cycle other than 50% to achieve the purpose of increasing the conversion gain, the most commonly used is a clock signal with a 25% duty cycle; however, the double frequency circuit (Doubler) requires a duty cycle...

AI Technical Summary

Problems solved by technology

[0006] Existing means for generating precise duty-cycle clock signals are limited and typically require a relatively large chip area and consume a large amount of current

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