A Realization Method of Vector Aggregate Load Instruction

Abstract

The present invention relates to the technical field of microprocessor design, and in particular to a method for implementing a vector aggregation load instruction. The corresponding element number is sent to the instruction queue; after the operand is ready, the single-element loading micro-operation is sent to the storage pipeline to obtain data; the obtained data is written into the corresponding element of the corresponding data cache item; all data cache items After the element data is written, the result data is written from the data cache to the result bus, and the execution of the vector aggregation load instruction is completed. The invention can effectively improve the execution performance of the vector aggregation load instruction, and at the same time can maximize the use of the path of the common load instruction, is suitable for high-performance out-of-order superscalar microprocessors, and has the advantages of simple implementation and high performance.

Description

technical field [0001] The invention relates to the technical field of microprocessor design, in particular to a method for realizing a vector aggregation load instruction. Background technique [0002] In order to adapt to the development of application programs and improve the efficiency of program execution, a variety of vector extensions have been added to mainstream instruction sets. Taking full advantage of the parallelism of vector operations can improve system performance. In vector extension, there is a type of vector aggregate load instruction (Gather Load, denoted as GLoad), which is very different from ordinary load instructions. Such as figure 1 As shown in (a) in (a), the ordinary load instruction loads the data of a continuous address in the storage space into the register. And for vector aggregate load instructions, such as figure 1 As shown in (b) in (b), the address of each element of the vector is different. This instruction needs to fetch an element f...

AI Technical Summary

Problems solved by technology

After splitting in this way, in addition to the Load operation for data acquisition, three Perm operations for data conversion are added, which increases the power consumption of instruction execution and the delay of instruction execution, resulting in performance degradation.

In addition, it is also necessary to increase the perm operation of data conversion in hardware design

[0005] The Chinese patent document with the application number 201810668398.4 discloses a launch method and device for mixed execution of scalar and vector instructions. This method can be used for launch and management of vector aggregate load instructions, but this method has the following three disadvantages: 1) The micro-operation management function of the vector buffer component and the launch queue function are duplicated, resulting in waste of resources

2) Since the vector buffer component has micro-operation management logic, the component resources are relatively large, which is limited by the hardware resources of the entire chip. The vector buffer component cannot support multiple vector aggregate load instructions at the same time, resulting in multiple vector aggregate load instructions that cannot be executed in parallel. , program performance is limited

3) Since there are instructions in the launch queue and the vector buffer unit to be sent to the pipeline, additional arbitration unit support is required, and the order management between instructions becomes complicated

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