Integrated circuit layout field domain identification and grid subdivision processing method and device

Abstract

The embodiment of the invention discloses an integrated circuit layout field domain identification and grid subdivision processing method and device. The method comprises the following steps: vertically projecting a plurality of polygons of each layer of integrated circuit layout to the same layer to form a Delaunay triangular grid; combining the polygon information and the layer information of the edges of the polygons which are superposed after projection; aligning the grids to the edges of each polygon, calculating the intersection points of the edges of each polygon, adding the intersection points into polygon vertexes and grid nodes to form a first triangular grid, forming a set by the edges of the polygons by an edge exchange method, taking out the edges of the polygons, exchanging the edges of the polygons, and if the set is a null set, ending the exchange; superposing the layer information of the edges of the polygons into all triangles in the polygons; identifying and collecting triangles and polygonal edges contained in each parallel flat plate field domain according to the layer information of the triangles and polygonal edges; and carrying out grid subdivision processing on triangles in each parallel flat plate field domain. According to the invention, the accuracy and high efficiency of the field domain identification and grid subdivision processing method can be ensured.

Description

technical field [0001] The invention relates to the field of integrated circuit layout field identification and grid subdivision processing, in particular to a method and device for integrated circuit layout field identification and grid subdivision processing. Background technique [0002] The layout of the integrated circuit is the intermediate link between the schematic diagram of the integrated circuit and the realization of the integrated circuit process, and it is an indispensable and important link. [0003] Since the thickness and layer spacing of the multilayer integrated circuit board are much smaller than the size of the board, the three-dimensional calculation field of the multilayer integrated circuit board can be simplified into multiple two-dimensional calculation fields, and the two-dimensional calculation field is the upper and lower layer The coupled parallel plate field is also the propagation area of ​​electromagnetic waves. The parallel plate field refe...

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Problems solved by technology

[0005] However, the inventor found in the process of implementing the present invention that in the prior art, in the process of field identification and mesh subdivision processing of the integrated circuit layout, the triangle mesh is aligned to each side of multiple polygons according to the edge exchange method In this case, it is easy to miss or repeat the exchange of edges of multiple polygons that meet the conditions, resulting in the accuracy, completeness and efficiency of the edge exchange method cannot be guaranteed, which in turn affects the field identification and grid detail. The Accuracy and Efficiency of Sub-processing Methods

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