Read-out circuit and working method thereof
A readout circuit and circuit technology, applied in the field of readout circuits, can solve the problems of increasing circuit area and cost, test structure interference, and high device requirements, and achieve the effects of complete coverage, shortened test time, and accurate test results.
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Embodiment 1
[0039] like figure 1 As shown, the present embodiment discloses a readout circuit 1, and the readout circuit includes: M columns×N rows of pixel circuits 12, N rows of row-level test resistor circuits 11, M columns of column-level test resistor circuits 13, and M columns Column-level readout circuit 14; wherein M and N are natural numbers and M≥2, N≥2;
[0040] The row-level test resistor circuit 11, the column-level test resistor circuit 13, and the column-level readout circuit 14 are all connected to the pixel circuit 12; the column-level test resistor circuit 13 is connected to the column-level readout circuit 12; The circuit 14 is connected; wherein, the column-level readout circuit 14 includes a test column sub-circuit; the column-level readout circuit 14 is also connected with a current source.
[0041] like figure 2 As shown, the present application discloses a detailed circuit of a readout circuit.
[0042] Preferably, the row-level test resistor circuit 11 include...
Embodiment 2
[0063] like image 3As shown, the present application discloses a structural schematic block diagram of a CMOS readout chip, including: M column × N row pixel array, N row test resistor circuit, M column readout circuit, row selection logic circuit, M column test resistor circuit . Test input and output circuits and data input and output circuits; wherein, columns 1 to (M-1) of the M column readout circuits are column-level readout circuits, and the Mth column is a test column.
[0064] like Figure 4 As shown, this embodiment discloses a readout circuit without a MEMS sensor; including: 1 column×N row level test resistor circuit, M column×N row pixel circuit, M column×1 row level test resistor circuit, M Column readout circuit; wherein, the M column readout circuit includes (M-1) column-level readout subcircuits and 1 column test column subcircuit;
[0065] Specifically, the row-level test resistor circuit, the readout circuit, and the column-level test resistor circuit are...
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