Field-effect transistor manufacturing method and field-effect transistor

Abstract

The invention discloses a field-effect transistor manufacturing method and a field-effect transistor. The method comprises the following steps of forming an N-type MOSFET region and a P-type MOSFET region on a substrate; forming a hard mask pattern on the MOSFET region; forming a silicon nanowire array structure; forming a sacrificial oxidization layer on the multi-layer stacked silicon nanowires,and then removing the sacrificial oxidization layer; carrying out selective SiGe epitaxy and concentration oxidation on the multi-layer stacked silicon nanowires of the P-type MOSFET region, and removing the oxidization layer; and sequentially forming an interface oxide layer, a ferroelectric material gate dielectric laminated layer and a metal gate laminated layer on the nanowire array structure. According to the field-effect transistor, the gate-control capability is greatly enhanced due to the ring gate structure; due to the PMOSFET SiGe nanowires and the SiGe source / drain, the hole mobility is greatly improved; and especially due to the fact that the ferroelectric negative capacitance effect is integrated, the potential on the surface of a channel of the device is amplified, so that the nanowire device has a super-steep sub-threshold slope and an improved on / off current ratio.

Description

technical field [0001] The disclosure belongs to the technical field of semiconductors, and relates to a manufacturing method of a field effect tube and the field effect tube. Background technique [0002] As the feature size of integrated circuits becomes smaller and smaller, planar CMOS devices have encountered serious challenges, and various new device structures have emerged. The gate structure of devices has evolved from traditional planar single gates to double gates, triple gates, and completely wrapped channel. The gate-enclosed structure, gate control ability and ability to control short channel effects are continuously enhanced, and MOSFETs with nanowire gate-enclosed structure (GAA) with quasi-ballistic transmission characteristics are widely used due to their strong gate control ability and size reduction ability. Attach great importance to it and become a strong competitor in the technology generation of 3nm and below. However, when the device size enters the t...

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Problems solved by technology

So far, the reported processes for fabricating SiGe nanowires are complicated, and the Damaccus pseudo-gate process using Si / SiGe alternating epitaxy is expensive, and the size reduction of nanowires has certain limitations.

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