A national cryptographic algorithm acceleration processing system based on an FPGA

A technology of national secret algorithm and processing system, applied in the field of national secret algorithm acceleration processing system, can solve problems such as poor scalability and low throughput rate, and achieve the effect of high throughput rate, good scalability, and good promotion and use value

Active Publication Date: 2019-06-18
北京中科海网科技有限公司
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Problems solved by technology

[0011] To sum up, the current hardware platforms for cryptographic accelerati...

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  • A national cryptographic algorithm acceleration processing system based on an FPGA
  • A national cryptographic algorithm acceleration processing system based on an FPGA

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Embodiment Construction

[0034] The technical solutions of the present invention will be further described below in conjunction with the accompanying drawings. These embodiments are used to illustrate the present invention without limiting the scope of the present invention.

[0035]National secret algorithms (SM2 / SM3 / SM4) are mainly used for encryption protection and security authentication of commercial information. With the development of high-speed networks, the demand for high-speed encryption and decryption of network data packets based on national secrets has become very urgent. However, the domestic encryption chips (Z8IDA chip, LKT4305 chip) in the current market adopt I 2 C bus transmission mode, the throughput rate is very low. Other publicly reported national secret hardware implementation schemes failed to achieve the throughput rate required by high-speed networks, and due to the limitations of their own system architecture, the scalability was poor, and it was inconvenient to expand int...

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Abstract

The invention discloses a national cryptographic algorithm acceleration processing system based on an FPGA. The system is used for processing a data packet which is sent to a server and needs to be processed by a national cryptographic algorithm. The system comprises an FPGA (Field Programmable Gate Array) accessed to a server through a PCIE (Peripheral Component Interface Express) core interface,wherein the FPGA is used for transmitting a data packet which is stored in the server and needs to be processed by a national cryptographic algorithm to a high-capacity cache DDR of the FPGA at a high speed through a PCIE core interface through DMA reading operation; The method comprises the following steps: processing a data packet needing to be processed by a national cryptographic algorithm through a corresponding national cryptographic algorithm IP core defined by a user, forming the data packet processed by the national cryptographic algorithm and transmitting the data packet to a DDR, and transmitting the data packet processed by the national cryptographic algorithm in the DDR to a server side memory through a PCIE core interface through DMA write operation. The acceleration processing system disclosed by the invention has good reusability and expandability, and has very good popularization and application values.

Description

technical field [0001] The invention relates to the field of network information security, in particular to an FPGA-based national secret algorithm acceleration processing system. Background technique [0002] With the continuous development of Internet technology, people are increasingly dependent on the network environment and network information resources, and information security issues have become the top priority of maintaining network security. The national secret algorithm issued by the National Security Bureau is a commercial encryption algorithm and specification independently developed by China, including the public SM2, SM3, and SM4 algorithms, which are used to ensure the security of commercial encryption. Today, more and more cryptographic chips are used in smart cards. How to effectively protect the security of smart cards through national secret algorithms and complete corresponding cryptographic tasks more efficiently has become a recent research hotspot in ...

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Application Information

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IPC IPC(8): G06F13/28G06F5/06
Inventor 宋曼谷郭志川黄逍颖宋磊
Owner 北京中科海网科技有限公司
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