Reading command acceleration method and device of NVMe SSD main control chip, computer equipment and storage medium

Abstract

The invention discloses a read command acceleration method and device of an NVMe SSD main control chip, computer equipment and a storage medium. The method comprises the steps that read data command information is cached in an acceleration module, and NFC is notified; the NFC reads corresponding data information from the flash according to the command information and sends the data information tothe acceleration module; and the acceleration module sends the processed valid data to the host. The limitation of the DDR reading and writing speed on the overall performance is avoided, and the usefrequency of a CPU is reduced, so that the data reading performance of the SSD main control chip is improved.

Description

technical field [0001] The present invention relates to SSD, more specifically to a read command acceleration method, device, computer equipment and storage medium of an NVMe SSD main control chip. Background technique [0002] The data path of the existing NVMe SSD main control chip is as follows: figure 1 As shown, when the host sends a read command through PCIe, the NVMe module caches the command and notifies the FW; after the FW parses the command, it notifies the NFC of the data information to be read, and the NFC outputs the data from the Flash to the DDR cache in random order. Perform reordering and remove redundant data; then the FW notifies NVMe to sequentially fetch the data from the DDR, sends them to the host through PCIe, and informs the FW after the current command is completed. [0003] The above method has the following problems: when the pipeline executes many commands, in order to cache the data of these commands, it needs to occupy a large amount of space...

AI Technical Summary

Problems solved by technology

[0003] The above method has the following problems: when the pipeline executes many commands, in order to cache the data of these commands, it needs to occupy a large amount of space resources in DDR; both NVMe and NFC must read and write DDR continuously, and the bandwidth requirement of DDR is too high. Bottleneck; the cooperation of NVMe and NFC requires the guidance of FW. For this reason, FW must be responsible for parsing PRP and checking the status of NVMe and NFC data transmission in real time, which increases the workload of CPU

These defects limit the speed at which NVMe SSD can read data, thus affecting the operating speed of the entire system

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