TSV array temperature optimization method based on an orthogonal test

Abstract

The invention discloses a TSV (Through Silicon Via) array temperature optimization method based on an orthogonal test, which mainly overcomes the defects of low efficiency and low precision of the existing three-dimensional integrated circuit temperature optimization technology, and comprises the following implementation steps of: setting a factor influencing the temperature of a TSV array; Selecting at least three factors as key factors; Selecting parameters for each key factor; Generating an orthogonal test table according to the selected factors and parameters; Establishing a through-silicon-via geometric model by utilizing finite element simulation software, arranging a test according to an orthogonal test table, and adding a result into the orthogonal test table; And determining the primary and secondary sequence of the temperature influenced by each factor, and designing an optimal scheme for reducing the temperature of the through-silicon-via array. Based on orthogonal tests andfinite element simulation, a test result with the precision higher than that of a traversal test can be obtained within the limited number of tests, the calculation time is greatly saved, large-scaledata processing is avoided, the temperature optimization efficiency and precision of the TSV array are improved, and the method can be used for designing a three-dimensional integrated circuit.

Description

technical field [0001] The invention relates to the technical field of microelectronics, in particular to a method for optimizing the temperature of a through-silicon via TSV array, which can be used in the design of a three-dimensional integrated circuit. Background technique [0002] As the feature size of the device gradually approaches the physical limit, it becomes more and more difficult to increase the integration level of the chip. The 3D integrated circuit based on through-silicon vias can provide vertical interconnection between chips, which greatly reduces the global interconnection length, breaks through the development bottleneck of two-dimensional integrated circuit interconnection delay and power consumption, and becomes a new technology for realizing high-density integration of systems. one of the key technologies. Although three-dimensional integration technology has many advantages, the chip temperature rise caused by its high device integration and high p...

AI Technical Summary

Problems solved by technology

Among them, the method based on the calculation of equivalent thermal conductivity has poor universal applicability. For different actual circuit structures, it is necessary to re-deduce the formula, and the workload is large, resulting in low efficiency; the method of inserting thermal vias can obtain the optimal The size structure needs to be traversed through parameter combinations, which is inefficient, and it is easily affected by random errors, and the accuracy is low

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