System for recovering PTP slave clock
A technology for restoring system and system configuration, applied in time division multiplexing systems, multiplexing communications, electrical components, etc. The effect of excellent retention characteristics
Inactive Publication Date: 2019-03-19
浙江赛思电子科技有限公司
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Problems solved by technology
However, this method has the problem that the obtained local clock rate and the master clock rate are too large. For example, affected by various factors such as the network environment, the PTP end-to-end transparent clock device sends each Sync message periodically to the master clock. It is impossible to forward strictly according to a specific period, and it can only roughly estimate the sending period of a Sync message, which makes it difficult to guarantee the accuracy of the dwell time
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Embodiment 1
[0020] Such as figure 1 As shown, a PTP slave clock recovery system meets the clock accuracy requirements of time synchronization devices in subway systems, high-speed rail systems, power systems, and transportation systems, including external standard reference source input modules, PTP modules, and local clocks Module, input signal processing and system clock frequency adjustment module, local standard clock signal generation module.
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Abstract
The invention provides a system for recovering a PTP slave clock. The system is characterized by comprising a PTP module, an input signal processing and system clock frequency adjusting module and a local clock module, wherein the PTP module marks a timestamp on a PTP data packet at a PHY layer (physical layer); when the system is configured as a main clock source, a high-precision and high-stability PTP is output, a PTP synchronization request is responded in a hardware level, and hardware automatically and regularly sends a PTP synchronization packet; when the system is configured as a slaveclock, a PTP synchronization event message and a general message can be received or sent, an optimal PTP main clock source is selected according to an optimal main clock source selection algorithm, and a time delay of a PTP synchronization line and a clock deviation between local and PTP main clock sources are calculated; the input signal processing and system clock frequency adjusting module isused for adjusting the frequency of a system clock signal, so that the system clock frequency is locked to an external standard reference signal or a PTP input; and the local clock module is used forproviding a local reference clock for the system to serve as a basis of system precision.
Description
technical field [0001] The invention relates to PTP synchronization technology, in particular to PTP time stamp acquisition, automatic sending of PTP synchronization packets and response to PTP synchronization request, clock frequency modulation and phase locking technology, in particular to a PTP slave clock recovery system. Background technique [0002] The PTP end-to-end transparent clock device, like a common bridge, router or switch, forwards all messages exchanged between the master clock device and the slave clock device. Typically, the dwell time bridge of the end-to-end transparent clock device will calculate the dwell time of the message passing through the device for the interactive PTP event message, and put the dwell time in a specific period of the PTP event message. Fields are accumulated, and after receiving the PTP event message, the slave clock device reads the dwell time and other timestamps carried in it to synchronize the clock. The time stamp (that is,...
Claims
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Patent Type & Authority Applications(China)
IPC IPC(8): H04J3/06
CPCH04J3/0638H04J3/0661
Inventor 许文管晓权田永和刘长羽叶泂涛王建鸿
Owner 浙江赛思电子科技有限公司
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