Semiconductor device and method of forming same

Abstract

The embodiment of the invention provides a semiconductor device and a method of forming the same. A static random access memory (SRAM) cell includes a first gate and a second gate each extending in afirst direction. A first gap separates the first gate from the second gate in the first direction. The SRAM cell includes a Vcc contact extending in the first direction. A second gap separates the Vcccontact and the first gate in a second direction perpendicular to the first direction. No segment of the Vcc contact overlaps with the first gap in the first direction. The SRAM cell includes a Vss contact extending in the first direction. A third gap separates the Vss contact from the first gate in the second direction. A segment of the Vss contact is disposed to the first gap. The Vss contact is smaller than the Vcc contact in the second direction.

Description

technical field [0001] Embodiments of the present invention generally relate to the field of semiconductors, and more particularly, to semiconductor devices and methods of forming the same. Background technique [0002] In deep submicron integrated circuit technology, embedded static random access memory (SRAM) devices have become popular storage units for high-speed communications, image processing, and system-on-chip (SOC) products. The amount of embedded SRAM in microprocessors and SOCs increases to meet the performance requirements of each new technology era. As silicon technology scales up from one generation to the next, the impact of intrinsic threshold voltage (Vt) variation on the smallest geometry bulk planar transistors reduces the static noise margin (SNM) of complementary metal-oxide-semiconductor (CMOS) SRAM cells . This reduction in SNM caused by smaller and smaller transistor geometries is undesirable. SNM is further reduced when Vcc is scaled down to lowe...

AI Technical Summary

Problems solved by technology

However, existing FinFET SRAM devices still suffer from disadvantages, such as those related to undesired variations in gate terminal positions, which can degrade gate / contact isolation and adversely affect FinFET SRAM performance and / or reliability

[0004] Therefore, while existing FinFET SRAM devices are generally adequate for their intended purposes, they are not yet fully satisfactory in every respect

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