Full-chip electrostatic discharge network
An electrostatic discharge, full-chip technology, applied in circuits, electrical components, electric solid devices, etc., can solve problems such as not helping to discharge electrostatic charges, affecting the anti-static ability of devices, etc.
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[0020] The full-chip electrostatic discharge network of the present invention, such as figure 2 As shown, it includes a power clamp circuit (PowerClamp) and multiple identical IO units connected in parallel.
[0021] The power supply clamping circuit is connected between the power supply and the ground, and the power supply clamping circuit also includes an ESD detection circuit for detecting ESD signals, and will generate a trigger signal after detecting the ESD signals; It also includes an electrostatic discharge transistor, and the detected ESD signal is simultaneously provided to the gate of the electrostatic discharge transistor. This transistor is used to release the static electricity on the power supply to the ground line, and this transistor is an NMOS transistor (BigNMOS) whose size is much larger than other transistors.
[0022] The multiple IO units include n identical units from IO(1) to IO(n), which are connected in parallel and then connected in parallel with ...
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