A convolution neural network accelerator based on PSoC

Abstract

This patent discloses a convolution neural network accelerator based on PSoC device, including an off-chip memory, a CPU, a feature map input memory, a feature Map Output Memory, a bias memory, a weight memory, a direct memory access to the same number of cells as neurons. The calculation unit comprises a first-in first-out queue, a state machine, a data selector, an average pooling module, a maximum pooling module, a multiplication and addition calculation module and an activation function module, wherein the calculations in the multiplication and addition calculation module are executed in parallel, and can be used for a convolution neural network system of various architectures. The invention fully utilizes the programmable part in the PSoC (Programmable System on Chip) device to realize the convolution neural network calculation part with large calculation amount and high parallelism, and utilizes the CPU to realize the serial algorithm and the state control.

Description

technical field [0001] The invention relates to convolutional neural network structure technology, in particular to a PSoC-based convolutional neural network accelerator. Background technique [0002] The convolutional neural network has unique advantages in image processing with local weight sharing. Its layout is closer to the actual biological neural network. Shared weights reduce the complexity of the neural network and reduce the computational load of the neural network. At present, convolutional neural networks are widely used in video surveillance, machine vision, pattern recognition, image search and other fields. [0003] However, the hardware implementation of convolutional network requires a lot of hardware resources, low bandwidth utilization and low data multiplexing. Convolutional neural networks need to support convolution operations of different sizes, pooling operations, and full connection operations. At the same time, many convolutional neural network app...

AI Technical Summary

Problems solved by technology

All the multiplication and addition calculations in the multiplication and addition calculation module are calculated in parallel, which supports convolution calculations of different convolution kernel sizes, and solves the problem of large calculation volume and large bandwidth requirements involved in the neural network.

The software partially solves the softmax classifier and non-maximum value suppression algorithm and image processing algorithm that cannot be realized by hardware logic, and solves the configuration of convolutional neural networks with different network structures

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