Design and implementation of programmable data plane exchange prototype based on P4

Abstract

The present invention belongs to the field of data plane exchanges, and discloses a design and an implementation of a programmable data plane exchange prototype based on a P4. A data plane employs anAXI4-Stream bus to achieve a pipeline architecture, perform sublevel processing for data entering a data passage, and each level on the pipeline is an independent IP core; a Verilog hardware description language development input arbitration module is employed to perform arbitration for 4 GE ethernet ports and a DMA channel data; P4-SDNet compiler is employed to a P4 appliance developed by the user to be compiled to an HDL model to achieve processing and forward of a data packet; and a Verilog hardware description language development output buffer queue module is employed to output the data packet to an external port. The user only needs to compile the compiled P4 appliance and to load the compiled P4 appliance to the system to achieve the network function described by the P4. Several development boards are employed to deploy a mini-type 4G network test system to have a certain practical value for teaching demonstration and scientific research usage of the P4.

Description

technical field [0001] The invention belongs to the field of programmable data plane switches, in particular to a P4-based programmable data plane switching prototype system. Background technique [0002] At present, the existing technologies commonly used in the industry are as follows: Software-defined networking (SDN) has achieved great success because it enables network owners and operators to program network behavior. However, its programmability is currently limited to the network control plane, and its forwarding plane is largely constrained by fixed-function packet processing hardware. P4 (Programmable Protocol-Independent Packet Processor) aims to completely get rid of the shackles of the network data plane, allowing network researchers to define the complete processing flow of data packets from top to bottom. Since the first P4 paper "P4: Programming Protocol-Independent Packet Processors" published on SIGCOMM CCR in 2014, P4 research has attracted great attentio...

AI Technical Summary

Problems solved by technology

However, the SUME board must be inserted above the host computer with the PCIE interface to realize the operation of the application software on the corresponding processor, which brings inconvenience to the construction of a network system with multiple P4 switches.

[0003] In summary, the problems in the prior art are: Existing P4 application testing methods are all simulated by bmv2 software switches and mininet tools, and cannot be deployed in a physical environment, resulting in a lack of accuracy and credibility in the verification results of the developed P4 application functions

However, the processor system and programmable switching chip of the P4 development platform launched by major manufacturers are independent of each other, and are realized by different devices, coupled with peripheral circuits, making the switch large in size and high in power consumption, which is very important in teaching demonstrations and scientific research. inconvenient

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