A stress-adjustable vertical structure LED chip and its preparation method

A LED chip and vertical structure technology, applied in the direction of semiconductor devices, electrical components, circuits, etc., can solve problems such as looseness, large difference in thermal expansion coefficient, bonding fragments, etc., to achieve good leakage prevention, avoid warping, The effect of reducing warping

Active Publication Date: 2021-01-26
HEYUAN CHOICORE PHOTOELECTRIC TECH CO LTD
View PDF6 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] It is found in the chip manufacturing process that there is a certain warpage or residual stress when the LED epitaxial layer grows on the silicon substrate, and some epitaxial wafer stresses are tensile stresses, such as figure 1 Shown; Some epitaxial wafers are under compressive stress, such as figure 2 As shown, then there will be such as in the bonding process Picture 1-1 and Figure 2-1 Bonding voids and warping, which will cause bonding fragments or weak bonding; at the same time, because the thermal expansion coefficients of Ag and GaN grown on the GaN layer are very different, during the annealing process of the Ag mirror It will introduce a large thermal compression stress, so it will also bring warpage or other adverse effects in the subsequent process

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • A stress-adjustable vertical structure LED chip and its preparation method
  • A stress-adjustable vertical structure LED chip and its preparation method
  • A stress-adjustable vertical structure LED chip and its preparation method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0065] refer to Figure 3-5 , a stress-adjustable vertical structure LED chip, including TiW-based back gold 10, Si substrate 1, bonding layer 2, first TiW-based protective layer 3, Ag-based reflector layer 4, LED epitaxy sheet and Ti / Al / W / Au n-electrode layer 8; the LED epitaxial sheet includes an n-type doped GaN layer 7 grown on a Si substrate, and an InGaN / GaN quantum well layer grown on an n-type doped GaN layer 6. A p-type doped GaN layer 5 grown on the InGaN / GaN quantum well layer.

[0066] The Si substrate takes the (111) plane as the epitaxial plane; the thickness of the n-type doped GaN layer is 1 μm, and the doping concentration is 1×10 18 cm -3 ; The InGaN / GaN quantum well layer is a 2-cycle InGaN well layer / GaN barrier layer, wherein the thickness of the InGaN well layer is 3nm, and the thickness of the GaN barrier layer is 5nm; the thickness of the p-type doped GaN layer is 100nm, doped The concentration is 3×10 17 cm -3 .

[0067] The method for preparing ...

Embodiment 2

[0077] A stress-adjustable vertical structure LED chip, which sequentially includes a TiW-based back gold layer, a Si substrate, a bonding layer, a first TiW-based mirror protection layer, an Ag-based mirror layer, an LED epitaxial wafer, and a Ti / Al / W / Au n electrode layer; LED epitaxial wafer includes n-type doped GaN layer grown on Si substrate, InGaN / GaN quantum well layer grown on n-type doped GaN layer, grown on InGaN / A p-type doped GaN layer on a GaN quantum well layer.

[0078] The Si substrate takes the (111) plane as the epitaxial plane; the thickness of the n-type doped GaN layer is 2 μm, and the doping concentration is 6×10 18 cm -3 ; The InGaN / GaN quantum well layer is a 14-period InGaN well layer / GaN barrier layer, wherein the thickness of the InGaN well layer is 4nm, and the thickness of the GaN barrier layer is 10nm; the thickness of the p-type doped GaN layer is 300nm, doped The concentration is 6×10 17 cm -3 .

[0079] The method for preparing the stres...

Embodiment 3

[0089] A stress-adjustable vertical structure LED chip, which sequentially includes a TiW-based back gold layer, a Si substrate, a bonding layer, a first TiW-based mirror protection layer, an Ag-based mirror layer, an LED epitaxial wafer, and a Ti / Al / W / Au n electrode layer; LED epitaxial wafer includes n-type doped GaN layer grown on Si substrate, InGaN / GaN quantum well layer grown on n-type doped GaN layer, grown on InGaN / A p-type doped GaN layer on a GaN quantum well layer.

[0090] The Si substrate takes the (111) plane as the epitaxial plane; the thickness of the n-type doped GaN layer is 5 μm, and the doping concentration is 9×10 18 cm -3 ; The InGaN / GaN quantum well layer is an InGaN well layer / GaN barrier layer with 18 cycles, wherein the thickness of the InGaN well layer is 10nm, and the thickness of the GaN barrier layer is 18nm; the thickness of the p-type doped GaN layer is 600nm, doped The concentration is 8×10 17 cm -3 .

[0091] The method for preparing th...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

PropertyMeasurementUnit
thicknessaaaaaaaaaa
thicknessaaaaaaaaaa
thicknessaaaaaaaaaa
Login to view more

Abstract

The invention discloses a stress-adjustable vertical structure LED chip, which sequentially comprises a TiW-based back gold layer, a Si substrate, a bonding layer, a first TiW-based mirror protective layer, an Ag-based mirror layer, and an LED chip from bottom to top. Epitaxial wafer and n electrode layer of Ti / Al / W / Au; LED epitaxial wafer includes n-type doped GaN layer grown on Si substrate, InGaN / GaN quantum well layer grown on n-type doped GaN layer, A p-type doped GaN layer grown on an InGaN / GaN quantum well layer. The invention also provides a preparation method of the stress-adjustable vertical structure LED chip. The vertical structure LED chip of the present invention uses sputtered TiW-based metal as a protective layer, and adjusts the growth stress of the LED epitaxial wafer, the stress released when the growth substrate is peeled off, and the stress released when the transfer substrate is thinned by adjusting the stress of the TiW-based metal. stress, reduce or avoid subsequent adverse effects.

Description

technical field [0001] The invention relates to the field of LED manufacturing, in particular to a stress-adjustable vertical structure LED chip and a preparation method thereof. Background technique [0002] With the gradual application of LEDs in the field of lighting, the market is no longer satisfied with the horizontal structure LEDs driven by small currents on sapphire substrates, and the application of vertical structure LEDs has emerged. Compared with the horizontal structure LED, the vertical structure LED can perfectly solve the poor thermal conductivity, current crowding effect and electrode light absorption effect of the horizontal structure by virtue of its P and N electrodes arranged on both sides, the current is vertically conducted, and the substrate is conductive. Capable of withstanding high current overdrive. The introduction of the reflector allows the vertical structure LED to emit light from one side, so that the external quantum efficiency of the vert...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Patent Type & Authority Patents(China)
IPC IPC(8): H01L33/46H01L33/36H01L33/32H01L33/06H01L33/00
CPCH01L33/0075H01L33/06H01L33/32H01L33/36H01L33/46
Inventor 李国强
Owner HEYUAN CHOICORE PHOTOELECTRIC TECH CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products