Floating gate memory unit and preparation method thereof

Abstract

The present invention relates to the field of semiconductor device manufacturing, in particular to a floating gate memory cell and a preparation method thereof. The method comprises the steps of forming a first sidewall thin film and a second thin film; after a plug is deposited in contact with an etch stop layer, removing the first sidewall thin film and the second sidewall thin film through plasma; forming an air-gap sidewall with the same feature as the sidewall; and forming a plurality of air gaps with the upper narrow and the lower wide, thereby overcoming the defects of crosstalk betweenthe floating gate memory cells and poor compatibility with the standard CMOS preparation process. The preparation method thereof in the invention effectively improves the read / write speed and the data maintaining ability of the memory cell, reduces the crosstalk between the floating gate memory cells, and improves the compatibility with the CMOS standard preparation technology.

Description

technical field [0001] The invention relates to the field of semiconductor device manufacturing, in particular to a floating gate memory unit and a preparation method thereof. Background technique [0002] The rapid development of the information age has brought about a large number of data storage requirements, which promote the rapid development of non-volatile storage technology. Floating gate storage (including NAND (NAND flash memory) and self-aligned source process NorFlash) has become the current mainstream non-volatile storage technology, widely used in data centers, mobile terminals, smart terminals and other fields, and still showing The situation of continuous and rapid growth of demand. [0003] When the semiconductor industry evolves the process technology below 45nm, as the physical size of the floating gate flash memory unit shrinks, the space on both sides of the floating gate also needs to be reduced to increase the density of the memory unit. However, the...

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Problems solved by technology

However, the process control is complicated, and it is necessary to form an air gap with a narrow top and a wide bottom with the inverted trapezoidal shape of the memory cell gate, which is poorly compatible with the standard CMOS manufacturing process.

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