Test method and system based on SPARC (Scalable Processor ARChitecture) processor single event upset fault injection

Abstract

The invention discloses a test system based on SPARC (Scalable Processor ARChitecture) processor single event upset fault injection. The system comprises a fault injection test data generation module,a fault injection automatic test execution module and a fault injection automatic test report output module. According to the system, defects and deficiencies that SPARC processor single event upsetfault types are various, fault injection special tests and fault injection precision control are deficient, and the manual operation efficiency under a hard platform test environment is low are solved. Fault injection is simulated through software, a model is established, injected single event upset faults are precisely monitored, and serialization operation is carried out. The system has the advantages that configuration scripts are stimulated flexibly, the all-digital simulation system modeling is operated at a high speed, the SPARC processor single event upset fault drive is simulated, andthe analysis and verification are carried out when the dynamic operation is carried out. The system has important significance in improving the China aerospace model software reliability and securityacknowledgement test and verification.

Description

technical field [0001] The invention relates to a testing method based on SPARC processor single-event flipping fault injection, and belongs to the technical fields of aerospace electronic technology and embedded software testing. Background technique [0002] In the space environment lacking the protection of the atmosphere, the spacecraft is directly exposed to the space radiation environment full of various high-energy particles. According to the distribution zone and particle source, the high-energy particles can be divided into earth-captured zone particles, solar cosmic rays, and galactic cosmic rays. . The impact of high-energy particles in the space radiation environment on semiconductor integrated circuits in spacecraft is mainly single event effects. In particular, single event upsets increasingly threaten the normal operation of spacecraft in orbit. The single event effect is the effect that high-energy particles are injected into a semiconductor device and form...

AI Technical Summary

Problems solved by technology

[0005] (1), the arrangement and combination of SPARC processor type, SRAM memory, EEPROM memory, non-writable area, and the single error, double error of fetching number and double error of fetching single event flip fault, resulting in various types of single event flip fault, exposing Insufficient ground test verification

[0006] (2) Lack of special tests for single-event faults, and test items such as single-error and double-error non-four-byte address alignment errors, boundary errors, frequent 0 and constant 1 errors, frequent errors, and master and backup errors to verify the tested items Insufficient robustness of the software

[0007] (3) Lack of precise control over the time interval, sequence, triggering moment, and fault sequence of single event upset faults

[0008] (4) Under the hard platform test environment, manual writing of fault-driven test cases one by one, serial port printing and output of actual test results, and manual writing of test reports are inefficient

The present invention solves the defects and deficiencies such as various types of single-event flipping faults of SPARC processors, lack of special testing for fault injection, lack of precise control of fault injection, and low efficiency of manual operation in hard platform test environments. Based on the characteristics of counting double faults and fetching double faults, a complete set of fault injection testing methods is proposed for spatial single event faults

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