FinFET-based master-slave flip-flop

Abstract

The invention discloses a FinFET-based master-slave flip-flop, comprising an input circuit, a master latch and a slave latch, wherein the input circuit comprises a first inverter, a second inverter and a third inverter, the master latch comprises a first FinFET transistor, a second FinFET transistor, a third FinFET transistor, a fourth FinFET transistor and a fourth inverter, and the slave latch comprises a fifth FinFET transistor, a sixth FinFET transistor, a seventh FinFET transistor, an eighth FinFET transistor, a fifth inverter and a sixth inverter. The scheme of the invention has the advantages that on the basis of realizing the correct working logic, a simple circuit structure is realized, a trigger function is achieved by adopting a small number of transistors, and in the working state, the working current is mainly composed of the current in the master latch and the current in the slave latch, the master latch and the slave latch work alternately, and thus without affecting thecircuit performance, the circuit area, power consumption and power-delay product are all small.

Description

technical field [0001] The invention relates to a master-slave flip-flop, in particular to a FinFET-based master-slave flip-flop. Background technique [0002] In the field of digital electronic technology, sequential logic circuits are composed of storage circuits and combinational logic, and storage components are used to maintain the logic state of sequential logic circuits. As a storage circuit, flip-flop is one of the basic circuits of digital circuits and plays an important role in digital circuit systems. [0003] With the continuous advancement of VISL technology, in the digital circuit system that does not require high operating speed, its power consumption requirements continue to increase, and the requirements for flip-flop performance are also more stringent. It is required that the flip-flop should have both low power consumption and low power consumption. Time-consuming delay product. The performance of the flip-flop's power consumption, power consumption del...

AI Technical Summary

Problems solved by technology

In the clocked D flip-flop, the internal structure of each two-input NAND gate in the master latch and the slave latch includes at least four Fin Field-Effect Transistors (Fin Field-Effect Transistors), The fin field effect transistor contained in each two-input NAND gate is in the common gate (Common Multi-Gate) working mode. Therefore, although the overall structure of the clocked D flip-flop is relatively simple, all the components in the overall structure The number of consumed FinFET tubes is large, the area is large, there will be large power consumption, and the power consumption delay product is also large, which is not conducive to the design of low-power circuits

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