A method of designing an integrated circuit with a porous dielectric layer

Abstract

The present invention relates to a method for designing an integrated circuit with a porous dielectric layer. The method controls an integrated circuit design tool (femtosecond laser device) through a computing device. The method does not require the use of a mask process, thus eliminating the need for a reticle. It breaks through the limitation of the mask plate, does not use toxic developing steps, and also saves the "blocking" process of the exposed pore structure of the porous medium layer, reduces the preparation process, shortens the preparation process, saves costs, and The stability and reliability of the semiconductor device are improved.

Description

technical field [0001] A method for designing an integrated circuit with a porous dielectric layer by implementing an integrated circuit design tool on a computing device, in particular a method for forming an integrated circuit by using a femtosecond laser device to etch a porous dielectric layer. Background technique [0002] The rapid development of semiconductor integrated circuit technology constantly puts forward new requirements for the development of interconnection technology. At present, in the back-end process of semiconductor manufacturing, in order to connect the integrated circuits composed of various components, metal materials with relatively high conductivity are usually used, but as the size of semiconductor devices continues to shrink, the interconnection structure becomes narrower and narrower. , resulting in higher and higher interconnect resistances. [0003] In the existing process of forming copper wiring or copper interconnection, trenches or via ho...

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Problems solved by technology

[0004] However, the use of low-K or ultra-low-K insulating dielectric materials poses new requirements for semiconductor manufacturing processes. On the one hand, in order to obtain low-K materials or ultra-low-K materials and reduce the K value of materials, the materials usually used are porous materials. However, the mechanical strength of porous materials is relatively low, which leads to easy damage to the insulating dielectric layer during the process of etching through holes or trenches. On the other hand, the porous insulating dielectric layer is easily infiltrated by external materials, causing pollution , reducing the reliability of the material

Existing academic studies have pointed out that the "open" pore structure exposed to the outside when etching the porous dielectric layer can be formed into a closed structure through an additional "plugging" process, so as to prevent metal impurities from easily forming an interconnection structure. However, the additional process not only increases the cost, but also easily changes the shape of the through hole or trench formed by etching, resulting in the unsatisfactory effect of the final interconnection structure; and In the process of etching through holes or trenches, the opening of the mask layer will be used to further etch to form a through hole or trench structure. In order to increase the precise formation of the opening, the mask structure usually used is a double-layer mask structure. When forming the opening of the mask layer, it is necessary to use photoresist to define the position of the opening first, and then expose and develop the photoresist to form the opening.

[0005] In this case, before etching the insulating dielectric layer, a step of forming a multi-layer mask layer, a step of forming a photoresist, and then a step of exposing and developing, and after etching to form an opening, the remaining The photoresist and the remaining mask layer removal steps are cumbersome. At the same time, the developer commonly used in the photoresist development process is a mixed solution of methyl isobutyl ketone + isopropanol, and these organic substances are toxic. Substances, dangerous if inhaled, not conducive to safe production

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