Iii-nitride field-effect transistor with dual gates

Abstract

A field effect transistor (FET) includes a III-nitride channel layer, a III-nitride barrier layer on the channel layer, a first dielectric on the barrier layer, a first gate trench extending through the first dielectric, and partially or entirely through the barrier layer, a second dielectric on a bottom and walls of the first gate trench, a source electrode on a first side of the first gate trench, a drain electrode on a second side of the first gate trench opposite the first side, a first gate electrode on the second dielectric and filling the first gate trench, a third dielectric between the first gate trench and the drain electrode, a second gate trench extending through the third dielectric and laterally located between the first gate trench and the drain electrode, and a second gateelectrode filling the second gate trench.

Description

[0001] Cross References to Related Applications [0002] This application is related to US Patent 8,530,978 issued September 10, 2013, US Patent 8,853,709 issued October 7, 2014, US Patent 8,941,118 issued January 27, 2015, and US Patent Application filed May 29, 2014 14 / 290,029, and is related to and claims priority from U.S. Provisional Patent Application 62 / 257,328, filed November 19, 2015, the entire contents of which are incorporated herein by reference. This application claims priority to and claims the benefit of US Patent Serial No. 62 / 257,328, filed November 19, 2015, which is incorporated herein by reference. [0003] Statement Regarding Federal Funding [0004] none. 【Technical field】 [0005] This invention relates to field effect transistors (FETs). 【Background technique】 [0006] A field effect transistor generally has a source electrode, a drain electrode, and a gate electrode that control the current flow between the source electrode and the drain electrod...

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Problems solved by technology

Threshold voltage shift is not desired

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