An overall fpga automatic layout method based on analytical methods

Abstract

An overall FPGA automatic layout method based on an analysis method, including: S1 packs and inputs constraint information and circuit netlist information through mapping; S2 inputs user-constrained delay information through a static delay analyzer; S3 inputs each circuit unit module According to the physical constraints specified by the user, the corresponding position in the physical design of the chip is automatically placed, including input and output layout, global clock layout, initial layout, overall layout, legalized layout and detailed layout; the overall layout is based on the initial position of the circuit unit module and The circuit topology connection is solved by the conjugate gradient method based on the hybrid step size adjustment strategy, and the step size calculation method is dynamically adjusted for different levels of circuit unit modules and layout states, and the circuit unit modules are distributed; S4 outputs circuit netlist information. The invention performs rapid and automatic layout on the chip layout, so that the line length and time delay of the line network meet the user's constraints; by adjusting the step size optimization strategy in the overall layout, the layout quality and speed are optimized.

Description

technical field [0001] The present invention relates to a kind of FPGA automatic layout method, specifically refers to a kind of overall FPGA automatic layout method based on analytical method, belongs to the field of integrated circuit design, especially belongs to a kind of semi-custom circuit FPGA (Field Programmable Gate) in the field of application specific integrated circuit Array, Field Programmable Gate Array) automatic layout related technical field category. Background technique [0002] FPGA adopts the concept of logic cell array (LCA, Logic Cell Array), and the internal circuit unit modules include: configurable logic module (CLB, Configurable Logic Block), input and output module (IOB, Input Output Block) and internal connection Line (Interconnect) and other parts. The FPGA chip is a two-dimensional structure, each point corresponds to a CLB, and each CLB contains a slice structure SLICE, and the SLICE contains a gate-level table (GATE). FPGA is a programmable...

AI Technical Summary

Problems solved by technology

At present, the scale of FPGA is getting bigger and bigger, and the structure is getting more and more complex. There are more and more types of logic unit modules, and it includes large devices such as DSP (Digital Signal Processor) and RAM (Random Access Memory). Logic units, and the wiring between some units are fixed connections, such as Carry Chain (carry chain) and Shift Register (shift register), etc., which limit the random placement of logic units, especially in timing In terms of constraints, since the layout plays a decisive role in the speed of the FPGA layout, the timing constraints must be taken into account during the layout process, otherwise it is difficult to meet the timing constraints through subsequent optimization such as routing.

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