Manufacturing method of semiconductor element

Abstract

The invention discloses a manufacturing method of a semiconductor element, which at least comprises the steps of firstly providing a substrate, wherein the substrate is internally defined with a storage region and a peripheral region, the storage region contains a plurality of storage units, each storage unit at least comprises a first transistor and a capacitor structure, the peripheral region contains at least one second transistor; then forming a first insulating layer in a mode of atomic layer deposition in the storage region and the peripheral region, wherein the first insulating layer atleast covers the capacitor structure of each storage unit in the storage region and the second transistor in the peripheral region; then forming a second insulating layer which covers the first insulating layer; and forming a contact structure in the second insulating layer in the peripheral region, wherein the contact structure is at least electrically connected with the second transistor.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing technology, in particular to a method for improving the problem of dielectric layer fragmentation in dynamic random access memory. Background technique [0002] Dynamic random access memory (DRAM for short hereinafter) is a main volatile memory, and is an indispensable key component in many electronic products. DRAM is composed of a large number of memory cells to form an array area for storing data, and each memory cell is composed of a metal oxide semiconductor (MOS) transistor connected in series with a capacitor. [0003] Wherein, the capacitor is located in the storage area, and there is a peripheral area beside the storage area, and the peripheral area includes other transistor elements and contact structures. Generally speaking, the capacitor located in the storage area has a larger height, so it has better charge storage efficiency, but at the junction of the storage area and th...

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Problems solved by technology

[0007] like figure 1 As shown, when the dielectric layer 120 is formed and cooled, if it is affected by additional stress, the dielectric layer 120 may crack

In this case, the contact structure 122 subsequently formed in the dielectric layer 120 will also cause the conductive layer in the contact structure 122 to flow to other places through these cracks because the dielectric layer 120 has many cracks, which may make the contact Structure 122 creates an open circuit and affects overall DRAM yield

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