Hash Partition Accelerator

Abstract

The invention discloses a Hash partitioning accelerator configured to be integrated on a memory and used for acceleration processing of a Hash connection partitioning stage. The Hash partitioning accelerator comprises a Hash unit, a histogram unit and a shuffle unit, wherein the Hash unit is used for reading multiple tuples in partitioned relation tables from a memory and then parallelly processing keys of the tuples to generate multiple Hash indexes; the histogram unit is used for parallelly updating multiple copies of histogram data stored in the histogram unit according to the Hash indexesand integrating all the updated copies into a histogram data form with data consistency; and the shuffle unit is used for determining positions of all the tuples stored in a target array according tothe Hash indexes, copying the tuples in the relation tables into the target array and realizing division of the relation tables. Through the accelerator, total energy consumption at the partitioning stage is remarkably lowered through acceleration at the memory end.

Description

technical field [0001] The disclosure relates to the field of computer systems, and further relates to a hash partition accelerator. Background technique [0002] The first factor to consider when designing a modern computer system is power consumption. To improve energy efficiency, hardware accelerators such as Field Programmable Gate Arrays (FPGAs), Graphics Processing Units (GPUs) and custom accelerators have been widely used in industry. With the advent of processing technology close to the data, integrating hardware accelerators into the dynamic random access memory (DRAM) stack to reduce the cost of data movement has become a new system design idea. The basic idea is to use 3D stacking technology to vertically integrate some logic dies including accelerators and multiple DRAM dies into one chip. However, the number and types of accelerators that can be integrated into DRAM are limited due to the limitations of 3D stacked DRAM in terms of area, power consumption, heat...

AI Technical Summary

Problems solved by technology

However, the number and types of accelerators that can be integrated into DRAM are limited due to the limitations of 3D stacked DRAM in terms of area, power consumption, heat dissipation, and manufacturing.

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