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Memory system performing error correction of address mapping table and method of controlling same

一种存储器系统、地址映射表的技术,应用在执行地址映射表的纠错的存储器系统及其控制领域,能够解决读写速度快、数据消失等问题

Active Publication Date: 2018-05-25
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Volatile memory devices have fast read and write speeds, but data stored in them disappear when power is interrupted

Method used

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  • Memory system performing error correction of address mapping table and method of controlling same
  • Memory system performing error correction of address mapping table and method of controlling same
  • Memory system performing error correction of address mapping table and method of controlling same

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Embodiment Construction

[0021] figure 1 is a block diagram illustrating a memory system 100 according to example embodiments. refer to figure 1 , the memory system 100 may include a memory controller 110 , a nonvolatile memory device 120 and a dynamic random access memory (DRAM) 130 . The memory system 100 can exchange data with a host through an input / output port. The memory system 100 may store data in or read data from the nonvolatile memory device 120 in response to a write or read request received from a host.

[0022] Controller 110 provides the physical connection between the host and memory system 100 . That is, the controller 110 may provide an interface between the host and the memory system 100 according to the bus format of the host. The controller 110 may drive firmware to control the memory system 100 . The controller 110 may include a central processing unit (CPU) 111, a working memory 112, a nonvolatile memory error correction circuit (NVM ECC) 113, a host interface 114, a mappin...

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PUM

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Abstract

A memory system performing error correction of an address mapping table and a method of controlling the same are provided. A memory system includes a nonvolatile memory device, a dynamic random accessmemory (DRAM) configured to store an address mapping table for an access to the nonvolatile memory device, and a controller configured to store, in the DRAM, the address mapping table that is dividedin units of address mapping data, each of the units having a size of an interface of the DRAM, read, from the stored address mapping table, target address mapping data corresponding to a logical address that is received from a host, the target address mapping data including a target parity and physical addresses of the nonvolatile memory device, and perform an error correction on the read targetaddress mapping data, using the target parity.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2016-0147679 filed on November 7, 2016 at the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference in its entirety. technical field [0002] Apparatuses consistent with example embodiments relate to a semiconductor memory device, and more particularly, to a memory system that performs error correction of an address mapping table. Background technique [0003] Semiconductor memory devices are broadly classified into volatile memory devices and nonvolatile memory devices. Volatile memory devices have high read and write speeds, but data stored therein disappear when power is interrupted. In contrast, nonvolatile memory devices retain data stored therein even if external power is interrupted. Therefore, a nonvolatile memory device is used to store information that is retained regardless of whether power is supplied. As a nonvolatile memory, flash memory is m...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/10G11C29/04
CPCG06F11/1016G06F11/1044G11C29/04G11C2029/0411G06F11/1048G06F2212/7201G06F2212/65G11C29/52G06F11/10G06F12/0292G06F11/1068G06F12/1009
Inventor 金贤植金泰焕
Owner SAMSUNG ELECTRONICS CO LTD
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