A Subthreshold SRAM Memory Cell Circuit Solving the Half-selection Problem

Abstract

The invention relates to a sub-threshold SRAM storage unit circuit for solving the half-selection problem, which belongs to the technical field of integrated circuits. In the memory cell circuit provided by the present invention, the first PMOS transistor MP1 and the first NMOS transistor MN1 constitute the first inverter, and the second PMSO transistor MP2 and the second NMOS transistor MN2 constitute the second inverter for storing opposite data. , two inverters form a feedback structure, so that the data can be latched stably; the sixth NMOS transistor MN6 and the seventh PMOS transistor MN7 are used to control the read operation, and the fifth NMOS transistor MN5 is used to solve the column half during the write operation. The stability of the storage point of the selected cell; since the third NMOS transistor MN3 or the fourth NMOS transistor MN4 is turned off during the write operation, the feedback loop of the two inverters is broken, so the cell write capability is greatly improved. The circuit of the present invention, combined with its read-write structure, can effectively improve the read-write noise tolerance; and can be effectively used in a bit-interleaved array structure to solve the half-selection problem; at the same time, the present invention works in the sub-threshold region, reducing power consumption.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits and relates to a sub-threshold SRAM storage unit circuit, which is especially suitable for solving the half-selection problem in a bit interleaved array structure. Background technique [0002] The sub-threshold design is gradually widely used because of its ultra-low energy consumption, especially for high-density integrated circuits such as SRAM (Static Random Access Memory, static random access memory). However, as the power supply voltage decreases, especially when the circuit enters the sub-threshold region, memory cells are more significantly affected by process fluctuations, resulting in reduced stability of memory cells and even errors, which place higher requirements on the design of memory cells . At the same time, with the continuous shrinking of the process size and the increase of the storage capacity, the soft error rate of the memory becomes higher and higher. The use ...

AI Technical Summary

Problems solved by technology

However, the use of the bit interleaving structure will cause half-selection problems, including the reduction of the stability of read half-selection and write half-selection, and even destroy the original storage state of the memory.

[0003] At present, the mainstream unit of SRAM is 6T structure, such as figure 1 Shown is a schematic diagram of the traditional 6T SRAM storage unit circuit structure. In order to make the 6T unit more stable, the size of the tube can be optimized, but the read and write capabilities of the optimized 6T unit are limited.

If the 6T unit is used in the bit-interleaved structure, the semi-selected unit will cause the transmission transistors N3 and N4 to open because the bit line WWL is at a high level, so the change of the bit line BL and BLB will affect the potential of the storage point, resulting in a half-selection problem.

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