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Multi-threshold-value unit replacing method based on hierarchical processing and cluster constraint

A layered, multi-threshold technology, applied in the direction of electrical digital data processing, special data processing applications, instruments, etc., can solve problems such as difficulty in adapting to the design environment, tight design cycle, and impossibility to achieve strong adaptability and portability capabilities, speed up design progress, and reduce design complexity

Active Publication Date: 2018-03-30
JIANGNAN UNIV
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Problems solved by technology

[0005] The algorithms published above mainly use customized cell libraries and customized timing analysis tools, which are difficult to adapt to different design environments. There are problems such as the need to build databases and format conversions. They are suitable for some simple combinational circuits, and it is difficult to cope with ultra-large-scale integration. Problems such as large scale and tight design cycle in circuit design
In addition, the traditional method (Synopsys Power Compiler User Guide, Version D-2010.03-SP2, 9-9:14) provides a method to optimize the static power consumption with the threshold cell ratio as a constrained parameter, which depends on the input threshold Unit ratio and constraint strength, it is impossible to automatically achieve a better balance between timing and static power consumption according to design constraints
Ran Fan et al. (Fan Ran, Dandan Zheng, Xiaolang Yan. An Algorithm for Reducing Leakage Power Based on Dual-Threshold Voltage Technique [C]. 2013 Fourth International Conference on Digital Manufacturing and Automation (ICDMA), 2013, 132–134) combined with EDA tools to re- The design process is planned, and threshold voltage values ​​are assigned to circuit nodes based on the timing results of static timing analysis. This optimization method is mainly suitable for designs with relatively loose timing constraints and low threshold voltage optimization timing paths. It is not suitable for high threshold voltage optimization. Consumable design

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  • Multi-threshold-value unit replacing method based on hierarchical processing and cluster constraint
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  • Multi-threshold-value unit replacing method based on hierarchical processing and cluster constraint

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Embodiment

[0047] Apply the multi-threshold unit replacement method of the present invention for testing.

[0048] The multi-threshold unit replacement method of the present invention takes the open source oc8051 core as an embodiment (https: / / opencores.org / projects).

[0049] First, use circuit synthesis software to synthesize the test circuit, add design constraints, convert the RTL-level code into a circuit netlist, and generate a design constraint file. Then, input the generated circuit netlist and design constraint files into static timing analysis software for static timing analysis. Finally, the optimization method described in the present invention is used in the static timing analysis software. The method is realized by Tcl script language, and after the method is executed, a file containing circuit nodes to be replaced is output for use in a subsequent ASIC design process.

[0050] image 3 , Figure 4 It is the result obtained after performing the above operations on the o...

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Abstract

The invention discloses a multi-threshold-value unit replacing method based on hierarchical processing and cluster constraint. The multi-threshold-value unit replacing method based on hierarchical processing and cluster constraint comprises the following steps: in parameter extracting stage, reading a parallel algorithm and a design constraint, counting combinational logic circuit nodes, and acquiring cell delay of the circuit nodes, static power consumption and a sequential path number; in a parameter analyzing and computing stage, computing cell delay variable quantity of the circuit nodes,static power consumption variable quantity and the ratio of the static power consumption variable quantity to the cell delay variable quantity; and in a to-be-replaced circuit node selecting stage, layering the circuit nodes on the basis of layering parameters, visiting the circuit nodes from the top layer to the bottom layer, tracing the worst timing sequence path of the circuit nodes, counting same-cluster circuit nodes in the time sequence path, setting a same-cluster circuit node priority and successively visiting the same-cluster circuit nodes, judging whether the circuit nodes meet design requirements or not, and outputting to-be-replaced circuit nodes. Selection of ASIC design to-be-replaced circuit nodes can be finished automatically, complexity caused by a traditional method is reduced, and the working efficiency is improved.

Description

technical field [0001] The invention belongs to the field of chip design automation, and in particular relates to a multi-threshold unit replacement method based on hierarchical processing and clustering constraints. Background technique [0002] The threshold voltage of a CMOS transistor is closely related to the leakage current, the larger the threshold voltage, the smaller the leakage current, and the smaller the threshold voltage, the larger the leakage current. In order to reduce the leakage current in the circuit unit, people have proposed a multi-threshold voltage technology, that is, transistors with different threshold voltages are used in circuit design. [0003] The design of multi-threshold voltage technology includes transistor-level design of multi-threshold units, research on the optimal threshold voltage difference under different power supply voltages, and optimization of multi-threshold unit circuits. Multi-threshold voltage technology mainly uses multi-th...

Claims

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Application Information

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IPC IPC(8): G06F17/50
CPCG06F30/398
Inventor 顾晓峰王亚军虞致国
Owner JIANGNAN UNIV
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