NoC (Network on Chip) error detection correction retransmission fault-tolerant method based on dual modular redundancy

Abstract

The invention relates to a NoC (Network on Chip) error detection correction retransmission fault-tolerant method based on dual modular redundancy. A source node sends a data packet to a target node, wherein the data packet comprises two same packet header microchips and a plurality of data microchips; after receiving the data packet, an intermediate node carries out error detection correction retransmission of dual modular redundancy on the packet header microchips, and transmits the correct packet header microchips and data microchips to a next node; and after receiving the packet header microchips and the data microchips, a target node carries out error detection correction retransmission on all the microchips. According to the invention, difference in importance in the data packet transmission process is utilized, error detection correction retransmission fault tolerance and dual modular redundancy fault tolerance are adopted, a fault-tolerant ability of a NoC is improved, reliability of data packet transmission can be ensured highly, and meanwhile, the NoC error detection correction retransmission fault-tolerant method gives consideration to performances of transmission delay,power consumption, effective data throughout and the like.

Description

technical field [0001] The invention relates to a NoC fault-tolerant method, in particular to a dual-mode redundancy-based NoC error-correction-detection-retransmission fault-tolerant method, which belongs to the field of integrated circuit multi-core design. Background technique [0002] With the continuous development of semiconductor and integrated circuit technology, the concepts of System-on-Chip (SoC) and Multicore Processors System-on-Chip (MPSoC) have been proposed, in order to solve the bottleneck of the bus architecture in MPSoC Problem, Network-on-Chip (NoC) was proposed, which is composed of IP core, local memory, router, network interface and link, to provide high reliability and low delay service for communication between components, while drawing on The multi-core network technology solves the problems caused by the bus architecture from the system architecture, and has the advantages of easy expansion, low verification complexity, and high utilization of band...

AI Technical Summary

Problems solved by technology

The traditional fault-tolerant method uses end-to-end error detection and retransmission or point-to-point error detection and retransmission to control the error of the data packet. This method cannot take into account performance requirements such as transmission delay, power consumption, and effective data throughput.

In addition, in applications with a relatively high error rate, the Baotou microchip is not specially protected, which further leads to performance degradation and even a high probability of error transmission

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