Method for conducting instruction dispatching based on network load features in data stream architecture

Abstract

The invention discloses a method for conducting instruction dispatching based on network load features in a data stream architecture. The method comprises the following steps of arranging a congestiondetection part inside each router-on-chip, arranging an output buffering part in each outlet of each router-on-chip, and arranging an instruction selection part inside each processing element; makingeach blocking detection part detect the blocking condition of each outlet of each router-on-chip and send the condition to the corresponding processing element in real time, wherein the blocking condition comprises a blocking state and a non-blocking state; making each instruction selection part select a priority scheduling instruction from an instruction slot and send the instruction to the corresponding router-on-chip, wherein the selection is conducted based on the condition that the instruction is in a 'ready' state and the outlet direction corresponding to the instruction is in the non-blocking state; making each router-on-chip temporarily store the received priority scheduling instruction to the output buffering part in the corresponding direction; making each route-on-chip send theinstruction to the next route-on-chip according to the target direction of the priority scheduling instruction which is temporarily stored in the corresponding output buffering part.

Description

technical field [0001] The invention relates to an instruction scheduling method in a data flow architecture, in particular to a method for executing instruction scheduling based on network load characteristics in a data flow architecture. Background technique [0002] With the development of computer architecture, domain-specific computer architecture has become the main development trend. When oriented to a specific application, the special-purpose structure uses the application characteristics to optimize the structure accordingly, so as to better exert the computing performance of the hardware. In the field of high-performance computing, data flow computing is an important branch of domain-specific computing structures, and data flow computing has shown good performance and applicability. The data flow architecture usually includes several or more than a dozen computing nodes (computing nodes are called processing elements, or PEs for short), and each computing node is ...

AI Technical Summary

Problems solved by technology

If instructions are mapped locally in a certain direction, according to the processing speed of the original on-chip routing, this direction will cause a bottleneck in the execution speed.

In addition, if the instruction is still scheduled according to the original polling strategy, it will cause the pause and idleness of the pipeline inside the computing node.

Images