Synchronous clock management module based on FPGA
A technology for managing modules and synchronizing clocks, which is applied to clocks driven by synchronous motors, synchronization, clocks, etc., can solve the problem of reducing system reliability, increasing the coupling relationship between software and hardware functional modules of the device, implementing complexity, and being unable to obtain second pulses, etc. problem, to achieve the effect of reducing overhead
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[0049] In the prior art, B code analysis, RTC clock and sampling pulse generation units are all independent, and there is a problem of complicated software and hardware design. However, this embodiment integrates three functional modules of B code analysis, self-synchronizing high-precision RTC, and self-synchronizing sampling pulse output on the FPGA chip. Each functional module can be used independently or in combination to organically combine the three , providing the CPU interface of the general bus to manage each module. The overall functional block diagram is as follows figure 1 As shown, FPGA-based delivery in the form of IP can meet various requirements for time synchronization and synchronous clock management of power grid security automatic devices.
[0050] The hardware main body of this embodiment is made up of a piece of FPGA (comprising supporting external circuit: power supply circuit and configuration circuit), a high-precision crystal oscillator (25M, 10PPM) a...
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