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Synchronous clock management module based on FPGA

A technology for managing modules and synchronizing clocks, which is applied to clocks driven by synchronous motors, synchronization, clocks, etc., can solve the problem of reducing system reliability, increasing the coupling relationship between software and hardware functional modules of the device, implementing complexity, and being unable to obtain second pulses, etc. problem, to achieve the effect of reducing overhead

Active Publication Date: 2018-01-12
NARI TECH CO LTD +3
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Problems solved by technology

However, this implementation method makes it impossible for each distributed unit to obtain the second pulse, and the whole system is completely dependent on the clock system of the main chassis, which reduces the reliability of the system
[0010] In order to realize the above functions on relay protection and safety automatic devices, it is necessary to carefully consider device architecture design, software function module division, and multi-module cooperation, which increases the coupling relationship and implementation complexity between the device software and hardware function modules

Method used

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  • Synchronous clock management module based on FPGA
  • Synchronous clock management module based on FPGA
  • Synchronous clock management module based on FPGA

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Embodiment 1

[0049] In the prior art, B code analysis, RTC clock and sampling pulse generation units are all independent, and there is a problem of complicated software and hardware design. However, this embodiment integrates three functional modules of B code analysis, self-synchronizing high-precision RTC, and self-synchronizing sampling pulse output on the FPGA chip. Each functional module can be used independently or in combination to organically combine the three , providing the CPU interface of the general bus to manage each module. The overall functional block diagram is as follows figure 1 As shown, FPGA-based delivery in the form of IP can meet various requirements for time synchronization and synchronous clock management of power grid security automatic devices.

[0050] The hardware main body of this embodiment is made up of a piece of FPGA (comprising supporting external circuit: power supply circuit and configuration circuit), a high-precision crystal oscillator (25M, 10PPM) a...

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Abstract

The invention discloses a synchronous clock management module based on an FPGA, and belongs to the technical field of electric power systems and automation of the electric power systems. The module includes a B code analysis submodule, a self-synchronizing RTC submodule, a self-synchronizing sampling pulse output submodule and an interface management submodule; all the submodules are integrated into one FPGA, and the B code analysis submodule, the self-synchronizing RTC submodule and the self-synchronizing sampling pulse output submodule can independently work. According to the module, the B code analysis submodule, the self-synchronizing RTC submodule and the self-synchronizing sampling pulse output submodule are integrated into one, the three submodules can work respectively, a completesolution is provided for synchronization clock management of a power-system relay protection and safety automatic device, the module is flexibly suitable for a variety of system implementation modes,the computation overhead of device CPU processing clock management is reduced, the software complexity is reduced, and the reliability of the whole device is improved.

Description

technical field [0001] The invention belongs to the technical field of electric power systems and automation thereof. More precisely, the invention relates to an FPGA-based synchronous clock management module. Background technique [0002] Clock management is an important function of grid safety automatic devices, mainly including the following aspects: [0003] 1) GPS-based time management, involving external B code signal analysis, quality analysis and abnormal monitoring; [0004] 2) When the device is charged, its own RTC timekeeping function, the time resolution is higher than 1ms; [0005] 3) The hardware system of the device needs to generate the trigger pulse used for electrical quantity sampling. When the device is composed of distributed multi-sampling modules, synchronous timing and synchronous sampling are required between the sampling modules, and synchronous triggering between the modules Pulse absolute time deviation is less than 10us; [0006] At present, ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G04G7/00
Inventor 颜云松朱传宏范腾徐军郭勋任建锋徐海波王计林陶翔李明应
Owner NARI TECH CO LTD
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