Network-on-chip architecture based on butterfly network coding and shortest path acquiring method of network-on-chip architecture

Abstract

The invention relates to the technical field of on-chip communication, in particular to a network-on-chip architecture based on butterfly network coding and a shortest path acquiring method of the network-on-chip architecture. The nodes of the network-on-chip architecture are distributed in a honeycomb manner, and each honeycomb is an equilateral triangle formed by the connecting lines of three adjacent nodes. The network-on-chip architecture has the advantages that the network-on-chip architecture based on butterfly network coding and Z-X-Y shortest-path routing matched with honeycomb topology can avoid deadlock and find out the shortest routing path; compared with traditional topological structures such as mesh topology, the honeycomb topology of the network-on-chip architecture has natural shortcuts and can reduce key link hop count; meanwhile, the network-on-chip architecture uses the butterfly network coding, can greatly eliminate network hot spots and can solve the problem of network congestion; the honeycomb network-on-chip architecture transmits data packets in a wireless manner and transmits control signals in a wired manner, data and the control signals are separated, and high-speed and efficient data transmission can be completed.

Description

technical field [0001] The invention relates to the technical field of intra-chip communication, in particular to an on-chip network architecture based on butterfly network coding and a shortest path acquisition method thereof. Background technique [0002] The key to the development of on-chip multi-core processors (CMP) is the communication architecture scheme between multiple cores. Under the traditional bus structure, on-chip communication technology has encountered a development bottleneck, and even if the characteristics of the transmission line are continuously improved, it is difficult to meet the inter-core communication requirements. In recent years, in order to improve the performance of on-chip communication, the scheme of replacing traditional bus technology with network-on-chip (NoC) has been proposed. Although the scalability of the traditional on-chip network interconnection structure based on metal dielectrics meets the requirements, it cannot meet the need...

AI Technical Summary

Problems solved by technology

Although the scalability of the traditional on-chip network interconnection structure based on metal dielectrics meets the requirements, it cannot meet the needs of future on-chip communication in terms of power consumption and interconnection speed; in order to solve the bottleneck problem of metal transmission lines, the wireless on-chip The characteristics of high transmission rate and low power consumption have gradually begun to be studied. Cheng Li et al. proposed a photon-on-chip network architecture using nanophotonic communication--LumiNOC; M.-C.F.Chang et al. proposed the use of guided wave transmission for On-chip network communication scheme; S.Watanabe et al. proposed UWB (Ultra Wideband) to carry out on-chip communication scheme; the proposed wireless on-chip network Small-Word (Small-Word) architecture uses wireless transmission to create a shortcut to reduce the critical path Delay, but as the size of the internal subnet increases, it will still lead to the emergence of high-latency paths

Moreover, if the inner network is too large, the problems of high delay and transmission rate reduction caused by wired transmission in the subnet are still difficult to solve

At the same time, the long distance of the wireless transmission interface and the inconsistency of the transmission distance of the wireless interface will lead to design difficulties

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