A Multi-way Server Interconnection Topology

Abstract

The invention provides a multipath server interconnection topological structure, which comprises a first single plate, a second single plate, a third single plate, a fourth single plate and a back plate, wherein the first single plate comprises a first processor, a second processor, a first processor interface, a second processor interface, a first connection interface and a second connection interface; the second single plate comprises a third processor, a fourth processor, a third processor interface, a fourth processor interface, a third connection interface and a fourth connection interface; and the third single plate comprises a fifth processor, a sixth processor, a fifth processor interface, a six processor interface and a fifth connection interface. The QPI (Quick Path Interconnect) buses of two processors on each single plate are subjected to partitioning processing, and cross interconnection parts do not need to mutually stride; and under a situation that normal work is guaranteed, the multipath server interconnection topological structure can realize even cooling, and a first connection area, a second connection area and a third connection area avoid connection cross routes among processors.

Description

technical field [0001] The invention relates to the server field, in particular to a multi-path server interconnection topology. Background technique [0002] As signal rates increase, signal integrity plays an increasingly important role in the efficient transmission of signals. There are many reasons that affect signal integrity, although engineers try to optimize and avoid all negative factors of signal integrity when designing at the board level. However, due to the long transmission of the interconnection architecture in the topological structure, the chip cannot bear such a large loss, reaching or even exceeding the design limit, which leads to the failure of the architecture to optimize the signal integrity of the bus. Contents of the invention [0003] In order to overcome the deficiencies in the above-mentioned prior art, the present invention provides a multi-channel server interconnection topology, including: a first single board, a second single board, a third...

AI Technical Summary

Problems solved by technology

However, due to the long transmission of the interconnection architecture in the topological structure, the chip cannot bear such a large loss, reaching or even exceeding the design limit, which leads to the failure of the architecture to optimize the signal integrity of the bus

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