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Method of optimization based on FPGA (Field Programmable Gate Array) high level synthesis (HLS) instructions and system thereof

A technology of high-level synthesis and optimization method, which is applied in the field of optimization method and its system based on FPGA high-level synthesis instruction, which can solve problems such as increased development difficulty, unknown instruction effect, and numerous adjustable parameters of HLS instruction, so as to shorten the development time. The effect of cycle and convenient development

Inactive Publication Date: 2017-09-19
FUJIAN NORMAL UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, due to the correlation and uncertainty of each source program, the large number of adjustable parameters of the HLS instruction, and the unknown effect of the instruction, the development is more difficult. This requires a general instruction optimization method to meet the current various requirements. Algorithms that require hardware acceleration

Method used

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  • Method of optimization based on FPGA (Field Programmable Gate Array) high level synthesis (HLS) instructions and system thereof
  • Method of optimization based on FPGA (Field Programmable Gate Array) high level synthesis (HLS) instructions and system thereof
  • Method of optimization based on FPGA (Field Programmable Gate Array) high level synthesis (HLS) instructions and system thereof

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Embodiment 1

[0091] Please refer to figure 1 and figure 2 , Embodiment 1 of the present invention is:

[0092] An optimization method based on FPGA high-level synthesis instructions, which can meet the versatility of various algorithms that require hardware acceleration, including:

[0093] S1. Preprocessing the source code of the source program. For example, through intelligent analysis and modification of source code, certain optimization strategies are adopted to remove dependencies to meet the requirements of parallel processing. HLS can be expanded in parallel within the loop and between functions. Since the logic operation and function parallelization between for loops will not be implemented during the scheduling process, in order to achieve parallel processing, it can only be placed in different functions. In addition, the processing of inline functions and data structures are all placed in the preprocessing optimization strategy.

[0094] S2. Perform parameter extraction on t...

Embodiment 2

[0110] Please refer to Figure 4 , Embodiment two of the present invention is a kind of optimization system based on FPGA high-level synthesis instruction, corresponding to the method of above-mentioned embodiment one, comprising:

[0111] The preprocessing module 1 is used to preprocess the source code of the source program;

[0112] The first extraction module 2 is used to extract parameters from the preprocessed source code;

[0113] An encoding module 3, configured to encode the extracted parameters;

[0114] Generating module 4, is used for setting the parameter after encoding, generates executable file;

[0115] Running module 5 is used to send the executable file into the HLS tool to run, and obtain the running result;

[0116] The second extracting module 6 is used to extract report data according to the operation result;

[0117] A judging module 7, configured to judge whether the operation result satisfies a preset condition according to the report data;

[0118...

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Abstract

The invention discloses a method of optimization based on FPGA (Field Programmable Gate Array) high level synthesis (HLS) instructions and a system thereof. The method includes: preprocessing source code of a source program; carrying out parameter extraction on the preprocessed source code; encoding parameters obtained by extraction; setting the encoded parameters, and generating an executable file; sending the executable file into an HLS tool to run to obtain a running result; extracting report-form data according to the running result; judging whether the running result meets a preset condition according to the report-form data; if yes, outputting the running result to obtain an optimization scheme; extracting a hardware description language according to the optimization scheme; and burning the hardware description language onto an FPGA development board. According to the method and the system, the generalities of various algorithms that need hardware acceleration can be met, carrying out relevant development by hardware and software developers can be facilitated, a development cycle of an FPGA hardware engineering project can be greatly reduced, and defects of traditional hardware description languages can be avoided.

Description

technical field [0001] The invention relates to the field of computer technology, in particular to an optimization method based on FPGA high-level synthesis instructions and a system thereof. Background technique [0002] In recent years, the upsurge of deep learning has continued to develop. When performing deep learning, the deep learning model has very high requirements for accuracy and computing power. Only by accelerating with better hardware can the requirements be met. FPGA (Field Programmable Gate Array, Field Programmable Gate Array) has the advantages of programmability and flexible configuration, and has greater advantages than GPU (Graphics Processing Unit, Graphics Processing Unit) which only focuses on calculation speed and fixed instructions. [0003] HLS (High Level Synthesis) tools overcome the disadvantages of traditional hardware description languages ​​such as difficulty in developing and long cycle times, allowing software developers to design better har...

Claims

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Application Information

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IPC IPC(8): G06F9/45
CPCG06F8/443
Inventor 黄晞陈宝林张仕郭升挺
Owner FUJIAN NORMAL UNIV
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