Efficient network IO processing method based on NUMA and hardware assisted technology

Abstract

The present invention discloses an efficient network I / O processing method based on the NUMA and the hardware assisted technology. The method is characterized in that in the virtualized environment, when an SRIOV (Single-Root I / O Virtualization) direct allocation device or a paravirtualization device generates a piece of physical interruption, by analyzing the CPU for processing the physical interruption, the target CPU and the node affinity of the NUMA (Non- Uniform Memory Access Architecture) where the underlying network card is located are interrupted; combined with the virtual CPU running information, interruption processing efficiency of the Intel APICv hardware technology and the Posted-Interrupt mechanism on the multi-core server is optimized; and under the condition that the context switching load caused by the VM-exit is fully reduced, all submission delays and call delays from generating interruption to processing interruption by the virtual machine are effectively eliminated, so that the I / O response rate of the virtual machine is greatly improved, and data packet processing efficiency of the data center network is greatly optimized.

Description

technical field [0001] The invention relates to the field of network virtualization, in particular to an efficient network IO processing method based on NUMA and hardware-assisted technology. Background technique [0002] Under the current cloud computing infrastructure architecture, the processing efficiency of the virtual network function integrated in the virtual machine is crucial to the efficiency of efficient network I / O processing. The existing DMA technology and zero-copy memory sharing mechanism greatly eliminate network I / O. / O data flow level load, the current main performance bottleneck is concentrated in the network I / O control flow level. NUMA (Non-Uniform Memory Access Architecture) architecture is a relatively mature multi-core processor architecture solution, which divides multi-core server hardware resources into multiple nodes (Nodes), each node has its own processor and memory resources, Among them, the speed of accessing the memory of the same node by t...

AI Technical Summary

Problems solved by technology

However, Intel APICv technology does not consider the underlying NUMA architecture of the current server and the network card, the CPU where the virtual machine management software resides, and the NUMA affinity of the interrupt destination CPU when submitting interrupts at the hardware level. The load balancing of virtual CPUs does not have a unified mechanism for cooperating with the Posted-interrupt interrupt delivery mechanism, which causes the notification interruption of the Posted-interrupt mechanism in a multi-core server to occur in the following two situations:

[0006] 1. When the CPU where the virtual machine management software resides is not on the same NUMA node as the CPU where the virtual machine resides, it takes a long time to notify the interrupt;

[0007] 2. After the interrupt information is written into the delivery interrupt descriptor of the destination virtual CPU and the interrupt is notified, the virtual CPU is transferred or scheduled to another physical CPU by the CFS scheduler, and the interrupt information will be delayed.

[0008] And the above two situations will affect each other, that is, the farther the NUMA "distance" of the two CPUs involved in the notification interrupt is, the worse the affinity is, and the more likely the virtual CPU will be transferred away by the scheduler

Therefore, this ignorance of the underlying NUMA architecture and the operating status of the virtual CPU restricts the improvement of the network I / O processing efficiency of the Intel APICv hardware technology.

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