Half-rate clock data recovery circuit

Abstract

The invention provides a half-rate clock data recovery circuit. The half-rate clock data recovery circuit comprises a voltage-controlled oscillator set to produce a data sampling clock and an edge sampling clock according to a control voltage; an adjusting circuit set to dynamically control the voltage-controlled oscillator to adjust a phase difference between the data sampling clock and the edge sampling clock to be different from 90 DEG in multiple testing periods; and a control circuit set to indicate the adjusting circuit to control the voltage-controlled oscillator in multiple testing periods by respectively utilizing different control value combinations, and record multiple recovery signal quality pointers respectively corresponding to multiple testing periods; and then the control circuit can indicate the adjusting circuit to control the voltage-controlled oscillator by use of a control value combination corresponding to an optimal quality pointer in the multiple recovery quality pointers.

Description

technical field [0001] The present invention relates to a half-rate clock data recovery circuit, in particular to a half-rate clock data recovery circuit that can dynamically change the delay of sampling signals. Background technique [0002] A traditional half-rate clock data recovery circuit uses a voltage-controlled oscillator to generate an in-phase clock signal and a quadrature-phase clock signal with a phase difference of 90 degrees. In the traditional half-rate clock data recovery circuit, the data sampling circuit will use the aforementioned in-phase clock signal as the data sampling clock of the input signal, while the edge sampling circuit will use the aforementioned quadrature phase clock signal as the edge sampling clock of the input signal . When the edge of the quadrature-phase clock signal is aligned with the edge of the eye diagram of the input signal, the edge of the in-phase clock signal should theoretically be aligned with the center of the eye diagram of...

AI Technical Summary

Problems solved by technology

[0003] However, in the actual application environment, due to the attenuation of the transmission medium, the eye diagram of the input signal is often not an ideal symmetrical shape, and the edge sampling circuit often has a certain data hold time (hold time)

In this case, using an in-phase clock signal and a quadrature-phase clock signal with a fixed phase difference of 90 degrees for sampling will cause the sampling position of the input signal to deviate from the optimal sampling point in the eye diagram when the loop is locked, resulting in data errors rate increase

Images