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A system and method for internal load balancing of SSD master control

An internal load and balance system technology, applied in the direction of program control design, multi-program device, climate sustainability, etc., can solve the problems of multi-CPU processing delay increase, to avoid delay increase, solve the problem of chip area and power The effect of wasting the problem

Active Publication Date: 2020-01-03
HUNAN GOKE MICROELECTRONICS
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AI Technical Summary

Problems solved by technology

[0007] The technical problem to be solved by the present invention is to provide a SSD master control internal load balancing system and method to solve the problem of chip area and power consumption faced by the hardware-oriented system design, and solve the usual software-based system solutions at the same time. In the process, the problem of increased delay caused by multi-CPU processing

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  • A system and method for internal load balancing of SSD master control
  • A system and method for internal load balancing of SSD master control
  • A system and method for internal load balancing of SSD master control

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Embodiment Construction

[0040] The present invention utilizes an IO command balance engine, which is responsible for distributing the IO commands from the HIF interface to each internal CPU, and each CPU is responsible for processing the received IO. Each CPU has a unique number within the system.

[0041] like figure 1 , each module function of the present invention is as follows:

[0042] HIF: Host Interface, the host interface, is responsible for receiving commands and data from the host, while returning a response to the host and transmitting data to the host.

[0043] NFC: Nand Flash Controller, NAND Flash controller, is responsible for completing command interaction and data transmission between SSD master control and NAND Flash.

[0044] IO Command Balance Engine: The IO command balance engine is responsible for completing the distribution of IO command requests from the HIF module to the internal CPU for processing, and forwarding the response from the internal CPU to the HIF. The IO comma...

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Abstract

The invention discloses an SSD main control internal load balance system and method. The balance system comprises a host interface, an NFC, an IO instruction balance engine and a plurality of CPUs, wherein the host interface is used for being responsible for receiving an instruction and data from a host, and returning response to the host and transmitting data to the host; the NFC is responsible for completing instruction interaction and data transmission between the SSD main control and an NAND Flash; the IO instruction balance engine is responsible for dispatching IO instructions from the host interface to the CPUs to be processed, and transferring response from the CPUs to the host interface; the multiple CPUs are responsible for performing dispatching processing on the IO instructions from the IO instruction balance engine and controlling data transmission. By adoption of the SSD main control internal load balance system and method, the problems of chip area and power consumption existing in preferable hardware type system design, and the problem of increasing time delay caused by multiple CPU processing in conventional software type system scheme are solved.

Description

technical field [0001] The present invention relates to SSD main control, in particular to an SSD main control internal load balancing system and method. Background technique [0002] The SSD master control is a key component of the SSD solid-state drive, and its processing performance determines the highest performance that the SSD solid-state drive can achieve. In recent years, the performance of enterprise-level PCIe SSD master control has entered the million-level IOPS. In the process of pursuing the ultimate performance of SSD master control, mainstream design manufacturers in the industry have mainly produced two architecture types: partial hardware type and logical RTL Realize FTL entry management of SSD main control, CPU is mainly used for various exception handling; partial software type, table entry management is mainly implemented by software, using very powerful CPU to support algorithm realization. [0003] The characteristic of hardware-oriented system design ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/50
CPCG06F9/5027Y02D10/00
Inventor 杨万云周士兵彭鹏马翼田达海
Owner HUNAN GOKE MICROELECTRONICS
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