Reconfigurable signal processor ASIC architecture and reconfiguration method thereof

Abstract

The invention relates to a reconfigurable signal processor ASIC architecture and a reconfiguration method thereof. The reconfigurable ASIC architecture comprises an RISC instruction parser, a configuration controller, a reconfigurable computing core, a data storage device, an MCB and a bus interface, wherein the bus interface, the RISC instruction parser, the configuration controller and the reconfigurable computing core are sequentially connected by virtue of a control bus to form a control channel, the MCB, the bus interface, the data storage device and the reconfigurable computing core are sequentially connected by virtue of a data bus to form a data channel. The ASIC architecture provided by the invention can be flexibly configured into multiple electronic countermeasure signal processors with low power consumption and high performance and is wide in application range and easy to use.

Description

technical field [0001] The invention relates to the technical field of reconfigurable design, in particular to a reconfigurable signal processor ASIC architecture and a reconfiguration method thereof. Background technique [0002] With the continuous development of digital chip design technology and the continuous improvement of chip manufacturing technology, more and more high-performance, low-power general-purpose processors are coming out. Although general-purpose processors such as CPU and DSP can be used for digital signal processing of electronic countermeasures, due to their versatility and the characteristics of running based on instruction streams, they consume a lot of power, area and processing time. [0003] Relatively speaking, ASIC (the English abbreviation of Application Specific Integrated Circuit, which is considered as an integrated circuit designed for a special purpose in the integrated circuit industry.) As a dedicated processing chip, its internal logic...

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Problems solved by technology

[0004] The technical problem to be solved by the present invention is to provide a reconfigurable architecture and method for digital signal processing applied to electronic countermeasures. In view of the current digital signal processing of electronic countermeasures, the power consumption, area, time, etc. of general processors are expensive, while ASIC Single application environment and poor applicability, a reconfigurable architecture that can implement multiple digital signal processing algorithms on ASIC

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