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Failure analysis method

A failure analysis and failure point technology, applied in electronic circuit testing, measuring devices, instruments, etc., can solve problems such as chip damage, tweezers bruises, scratches, etc.

Inactive Publication Date: 2017-01-18
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0009] There is a big disadvantage of using these two methods, that is, the chip will be damaged to varying degrees during the sample preparation process, such as being bruised by tweezers, scratched, grinded, gold wire, etc.
In this way, it is difficult to distinguish whether it is a process problem of the packaging factory or a problem of sample preparation.

Method used

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Embodiment Construction

[0034] In order to make the content of the present invention clearer and easier to understand, the content of the present invention will be described in detail below in conjunction with specific embodiments and accompanying drawings.

[0035] Figure 2 to Figure 4 Schematically shows the structure diagram of each step of the failure analysis method according to the preferred embodiment of the present invention. The failure analysis method according to the preferred embodiment of the present invention can be used for failure analysis of integrated circuit chip samples.

[0036] Specifically, as Figure 2 to Figure 4 As shown, the failure analysis method according to the preferred embodiment of the present invention includes:

[0037] The first step: grinding the packaging glue 1 on the back side of the packaging sample until the chip pad 2 is exposed;

[0038] Specifically, generally, the encapsulation glue 1 is encapsulation black glue.

[0039] For example, if figure 1 A...

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Abstract

The invention provides a failure analysis method. The method comprises the steps that 1) a packaging adhesive at the back side of a packaged sample is ground till that a chip bonding pad is exposed; 2) a silver colloid under a chip and the chip bonding pad are removed; 3) grounding is carried out to expose the frame edge corresponding to pins which need testing; and 4) a positioning device is used, point pins are used to carry out back-side failure positioning analysis on the chip on the exposed lead frame so as to find failure points.

Description

technical field [0001] The invention relates to the fields of semiconductor manufacturing and failure analysis, more specifically, the invention relates to a failure analysis method. Background technique [0002] Packaged samples (such as figure 1 ) In product-level testing, or when failures occur on the customer application side, it is often necessary to perform failure analysis on these samples. If it is a process problem, it is necessary to distinguish whether it is from the wafer factory or the packaging factory. [0003] In addition, the failure location of packaged samples is a very important step in this type of failure analysis. However, due to the continuous increase of chip metal layers, failure location from the back of the chip, that is, the direction of the silicon substrate, has become the mainstream. As for the packaged chip, there are opaque silver glue, metal chip pads, black glue and other materials on the back of the chip, so these materials must be remo...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/28
CPCG01R31/2898
Inventor 陈强高金德
Owner SHANGHAI HUALI MICROELECTRONICS CORP
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