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LDPC/Turbo code dual-mode decoder

A technology of LDPC code and decoder, applied in the direction of coding, code conversion, coding components, etc., can solve the problems of different decoding algorithms, different hardware structures of single-mode decoders, waste of resources, etc.

Inactive Publication Date: 2017-01-04
CHINA JILIANG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the decoding algorithms of LDPC code and Turbo code are different, which will lead to the difference in the hardware structure of the single-mode decoder. If the single-mode decoder is simply combined into a dual-mode decoder, it will definitely cause a waste of resources.

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  • LDPC/Turbo code dual-mode decoder
  • LDPC/Turbo code dual-mode decoder
  • LDPC/Turbo code dual-mode decoder

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Embodiment Construction

[0020] The LDPC / Turbo code dual-mode decoder of the present invention comprises an input cache, a demultiplexing unit, a posteriori information (Lall) storage unit, a data reorganization interleaving network, a SISO array, an external information (Lmd) storage unit, a lower Second iteration (NII) unit, hard decision output unit and control unit, what the Lall storage unit and the Lmd storage unit of described LDPC / Turbo code dual mode decoder adopted is the mode of storage unit splicing and SISO decoding unit is based on CFU unit is designed.

[0021]The Lall storage unit of the present invention is used for storing Turbo channel information, LDPC code channel information and posteriori information. When performing LDPC decoding, the channel information is written into the Lall storage unit in columns. When Turbo decoding is performed, the channel information is first demultiplexed to output system information bits, check 1 and check bit 2 information, and then stored in the ...

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Abstract

The invention discloses a LDPC / Turbo code dual-mode decoder. The decoder comprises an input buffer, a de-multiplexing unit, a posteriori information storage unit, a data reconstitution interlacing network, a SISO array, an outer information storage unit, a next iteration unit, a hard decision output unit and a control unit. The SISO array is formed by 12 SISO decoding units. The SISO decoding units are main calculating units of the dual-mode decoder and are designed based on a configurable dual-mode calculating unit. A code length difference of a LDPC code and a Turbo code is large. If a design is performed according to code length maximization, resource wastes are generated. And the above problem is solved through using a storage unit splicing mode by the posteriori information storage unit and the outer information storage unit. In the invention, dual-mode decoding of the LDPC and Turbo codes can be realized, and resource sharing of two aspects of the calculating units and the storage units is realized too.

Description

technical field [0001] The invention relates to the field of modern communication systems, in particular to the technical field of channel coding and decoding, and in particular to an LDPC / Turbo code dual-mode decoder capable of decoding both LDPC codes and Turbo codes. Background technique [0002] In a modern communication system, the information to be transmitted can be corrected by encoding, modulation, channel transmission, demodulation and decoding. The decoder acts on the above-mentioned decoding process. The excellent performance of LDPC codes and Turbo codes makes many communication standards choose these two codewords as channel coding schemes or alternative schemes. In future communication systems, LDPC and Turbo codes are also indispensable schemes. Multi-mode error correction decoders play an important role in the exchange of information between different communication networks. However, the decoding algorithms of LDPC code and Turbo code are different, which ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M13/11H03M13/29
CPCH03M13/1108H03M13/2966
Inventor 王秀敏曹维林李婷婷宿晨李正权
Owner CHINA JILIANG UNIV
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