Method for solving read delay uncertainty of hybrid memory

Abstract

The invention discloses a method for solving read delay uncertainty of a hybrid memory and relates to the field of hybrid memories. The method comprises the steps of providing a hybrid memory comprising a dynamic random access memory (DRAM) and an SCM for communication connection, wherein the DRAM includes a main distribution area and a tail end distribution area according to storage unit retention time; and placing read-heavy or write-heavy data in the DRAM tail end distribution area which is to be replaced with the SCM, wherein the hybrid memory prestores an address lookup conversion table and the address lookup conversion table includes mapping items of DRAM addresses and SCM addresses which are subjected to replacement storage. It is not an easy thing to solve the problems of internal memory bottleneck and power consumption bottleneck; however, through cross effects of all aspects, such as technical formula, novel design of the memory, structure innovation and system support, a possible opportunity still remains, or even the DRAM, a storage controller and an operating system do not need to be modified. Along with difference reduction of the DRAM and the SCM on page read delay, the pulse code modulation (PCM) access difference within a fixed period will disappear.

Description

technical field [0001] The invention relates to the field of hybrid memory, in particular to a method for solving the uncertainty of read delay of the hybrid memory. Background technique [0002] In the prior art, a hybrid memory method is used to improve the performance of the DRAM and reduce refresh power consumption by adding a non-volatile new memory (New Concept Memory, NCM) to the DRAM. In the non-busy state of the DRAM, the data stored in the storage unit in the distribution area at the end of the DRAM is transferred to the new memory, and then the refresh cycle of the DRAM is increased, thereby greatly reducing the refresh power consumption of the DRAM and improving the performance of the DRAM. The implementation of the hybrid memory read operation can store the mapping relationship between the DRAM address and the NCM address through the address lookup conversion table, and control the data output from the DRAM or NCM according to the matching result through the mat...

AI Technical Summary

Problems solved by technology

[0003] Since the read delay of storage class memory (Storage Class Memory, SCM) is very different from that of DRAM, in fact, the read delay of SCM is 4 times that of DRAM, which makes the read of SCM incompatible with the original DDR protocol. Therefore, In the application scenarios of LPDDR and mobile devices, it is necessary to consider how to solve the problem that the read delay of SCM is too large

Another problem is the uncertainty of the read delay. In the read operation, if the read data comes from the SCM, then the conventional DRAM timing cannot be satisfied, because the current DDR protocol only supports definite read and write. Timing, this non-deterministic read delay will cause conflicts on the data bus