Nanosecond grade digital synchronizer based on FPGA high-speed serial bus

Abstract

The invention discloses a nanosecond grade digital synchronizer based on a FPGA high-speed serial bus. The digital synchronizer comprises a starting signal module, a signal isolation module, a FPGA control time sequence module, a signal conversion module and a pulse signal output module which are electrically connected in order; the FPGA control time sequence module is connected with an upper computer through a 422 serial port module; the technical scheme implement the synchronous triggering and pulse width modulation of multipath pulses with delay precision of 1ns, the digital synchronizer is small in volume, wide in delay range, adjustable in pulse width, and capable of meeting different requirements of synchronous triggering of a plurality of large physical devices.

Description

technical field [0001] The invention relates to the technical field of digital control, in particular to a nanosecond-level digital synchronization machine based on FPGA high-speed serial bus. Background technique [0002] In large-scale high-energy physics scientific experiments, due to the influence of installation location, operating environment, and other factors, and the length of transmission cables for each synchronous trigger signal is different, each trigger signal has a delay and cannot arrive synchronously. To solve the high-precision synchronous triggering of multiple physical experiment devices or multiple channels, it is necessary to develop a multi-channel digital synchronization machine. [0003] The current delay synchronization machine has the following problems: (1) It is realized by artificially adjusting the length of the transmission cable of each signal. This method is cumbersome, the accuracy is not high, and the delay cannot be automatically controll...

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Problems solved by technology

[0002] In large-scale high-energy physics scientific experiments, due to the influence of installation location, operating environment, and other factors, and the length of transmission cables for each synchronous trigger signal is different, each trigger signal has a delay and cannot arrive synchronously. To solve the high-precision synchronous triggering of multiple physical experiment devices or multiple channels, it is necessary to develop a multi-channel digital synchronization machine

[0003] The current delay synchronization machine has the following problems: (1) It is realized by artificially adjusting the length of the transmission cable of each signal. This method is cumbersome, the accuracy is not high, and the delay cannot be automatically controlled and adjusted; (2) 2007 "Research on High-precision Digital Synchronizer for Ultra-short Laser Pulse Technology" in December 2009, using 8253 counters and analog interpolation delay technology to achieve high-precision delay with a delay accuracy of 1ns, and the output pulse Shake value ≤ 500ps, using the counter method to achieve 1ns delay accuracy, the operation process is too complicated

[0004] The delay accuracy of the utility model of CN201893762.U is 1ns, but from the technical scheme of realization, the utility model of CN201893762.U is realized by the method of FPGA+high-precision digital delay line, and the area of ​​the device is relatively large. And the delay range is narrow

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