Chips and Electronic Devices

Abstract

The present invention provides an electronic device, which includes a carrier circuit board, and a chip loaded on the carrier circuit board. The chip includes a packaged substrate and a bare chip. The wiring of the substrate corresponding to the bonding point, the solder joints in the solder joint matrix at the bottom of the substrate include the first solder joint group and the second solder joint group respectively arranged along two parallel straight lines, and the first solder joint group and the second solder joint group The substrate traces connected to the solder joints are of equal length, and the substrate traces connected to the solder joints in the second solder joint group are of equal length, and the length difference between the two substrate traces is equal to the preset standard value. There are pads corresponding to the pads of the first pad group and the pads of the second pad group, and circuit board traces are connected to the pads, and the pads on the pads corresponding to the first pad group The length difference between the circuit board trace and the circuit board trace on the pad corresponding to the second pad group is equal to the preset standard value.

Description

technical field [0001] The embodiments of the present invention relate to chip technology, and in particular to a chip and an electronic device loaded with the chip. Background technique [0002] With the continuous development of integrated electronic technology, the operating frequency of the chip is getting higher and higher, and the requirements for the timing relationship of signals are becoming more and more stringent. For a high-speed transmission signal, such as a DDR (Double Data Rate, double rate) signal, the timing relationship directly affects the signal quality. If the chip input timing deviation in the board exceeds the design standard, the input command will not be executed. In order to ensure that the chip can work stably, the timing deviation between signals must be as small as possible. This requires chip designers to design circuits not only to achieve basic functions, but also to control the timing of signals as much as possible. The transmission of si...

AI Technical Summary

Problems solved by technology

like figure 1 In such an arrangement method, a large amount of wiring space must be reserved in the chip substrate 14 and the printed circuit board 17, especially the small size of the substrate 14 has limited wiring space, and more wiring layers may be required to realize the wiring of signal lines, etc. Long control, which will lead to an increase in the number of substrate layers, which is not conducive to the cost control of the chip

Moreover, electronic equipment manufacturers need to use various means to obtain the delay of each path on both sides of the chip and the printed circuit board, and set up wiring for each path separately, which greatly increases the production and design costs of electronic equipment.

Images