Novel P<+> sidewall non-junction field effect transistor

Abstract

The invention discloses a P<+> sidewall non-junction device. The P<+> sidewall non-junction device consists of dual gates, a source region, a drain region, a channel region, gate dielectric layers, P<+> sidewalls and isolation layers. For a conventional non-junction device, when the length of a gate is reduced to 10nm, a leakage current is greatly increased, so that the inhibition of the magnitude of the leakage current becomes an important task of a small-sized device. For the conventional non-junction device, a turn-off current of the device in a turn-off state cannot be effectively controlled only by the control capability of the gate. According to the P<+> sidewall non-junction device, PN junction depletion can be formed for assisting in depletion of the device, and when the device is turned on, the gate controls a P<+> region for weakening the PN junction depletion, so that a turn-on current is not influenced. Compared with the conventional non-junction device, the novel P<+> sidewall tri-gate nanowire non-junction device has great advantages, and the advantages are especially remarkable when the gate is very short. The novel device mainly can improve the characteristics of a sub-threshold slope, a turn-on and turn-off current ratio and the like of the conventional non-junction device.

Description

technical field [0001] The invention relates to a device for semiconductor integrated circuits, mainly a novel P+ side wall junctionless field effect transistor. Background technique [0002] As the size of the device decreases, the leakage current of the device will gradually increase, which causes a great degradation of the characteristics of the device. Therefore, finding ways to reduce the leakage current of small junction-free devices has become a top priority. There are few methods that can reduce the leakage current of the device, and the more common one is to increase the control ability of the gate. In addition to the modification of the device gate, we hope that the leakage current of the junction-free device can be reduced through the modification of the side wall of the device. Sidewalls usually use SiO 2 and other materials to isolate the gate and source and drain regions. We hope that the sidewall can play a greater role in device cut-off. By modifying the...

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Problems solved by technology

However, despite the use of high-K materials, the gate's ability to control this part of the extra channel is very limited. When the device gate continues to shrink, the leakage current control is still not enough

[0005] Based on the understanding and mastery of the sidewall structure of junction-free devices, we found that whether it is a high-K material sidewall or other structural sidewalls, the leakage current control of junctionless devices is very limited and cannot form greater control. ability

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