Semiconductor device and manufacture method thereof

Abstract

The invention relates to a semiconductor device. The semiconductor device includes a plurality of fin structures which vertically protrude out from a substrate and extend along a first direction, source and drain regions which are formed at two ends of each fin structure along the first direction, channel regions which contain a plurality of nanowires and are connected between the source and drain regions along the first direction, and a gate stack structure which extends along a second direction and surrounds each nanowire. According to the semiconductor device and the manufacture method thereof, the channels of nanowires are formed between the fin-shaped source and drain regions, and therefore, process cost can be decreased, process complexity can be reduced, and grid control ability and device density can be effectively improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a Fin Field Effect Transistor (FinFET) with a nanowire channel and a manufacturing method thereof. Background technique [0002] In order to meet the challenges brought by the continuous miniaturization of semiconductor devices, a variety of high-performance devices have been proposed, especially in the current sub-20nm technology, three-dimensional multi-gate devices (FinFET or Tri--gate) are the main device structures , this structure enhances gate control capability, suppresses leakage and short channel effects. [0003] For example, compared with the traditional single-gate body Si or SOIMOSFET, the double-gate SOI MOSFET can suppress the short-channel effect (SCE) and drain-induced barrier lowering (DIBL) effects, and has lower junction capacitance. The channel is lightly doped, and the threshold voltage can be adjusted by setting the work function of the metal gate,...

AI Technical Summary

Problems solved by technology

However, the nanowire process requires the formation of additional pad supports, which requires extremely high precision and mechanical property control of the device etching process

In addition, in order to enhance the gate control capability, the gate above the nanowire channel is often a metal gate manufactured through a gate-last process, which is complex and expensive

Furthermore, in order to support the pad structure, the source and drain regions often occupy a large area in plan view, which affects the integration of devices.

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