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Cell Array Computing System

A cell array and computing system technology, applied in the field of cell array computing systems, can solve problems affecting computer performance and poor cost-effectiveness ratio, and achieve the effect of improving overall performance and good cost-effectiveness ratio

Active Publication Date: 2019-02-19
SHANGHAI CIYU INFORMATION TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0009] The problem to be solved by the present invention is that the computer architecture in the prior art affects the improvement of the overall performance of the computer due to the communication bottleneck between the CPU, memory and storage, and makes the cost-effectiveness relatively poor

Method used

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  • Cell Array Computing System
  • Cell Array Computing System
  • Cell Array Computing System

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0056] Such as figure 2 As shown, the cell array computing system provided in this embodiment includes: a main control CPU, a cell array, and a cell array bus; the cell array is the main body in the cell array computing system, and it is composed of more than one A two-dimensional array of functional cells, each of which includes a microprocessor (MPU) and non-volatile random access memory ( figure 2 MRAM is used as an example); the non-volatile random access memory is used for the random access of data involved in the calculation of the microprocessor, and is also used to store software instruction codes and data that need to be permanently preserved; each cell stores Each position in the cell array is used as an ID for software or hardware in the cell to read; the main control CPU communicates with each cell in the cell array through the cell array bus; the cell array There are communication interfaces between adjacent cells in the cell and can send data to each other.

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Embodiment 2

[0175] Based on the cell array computing system provided in Embodiment 1 of the present invention, the cell array computing system provided in this embodiment extends a two-dimensional cell array to a three-dimensional cell array.

[0176] Such as Figure 14 As shown, the cell array computing system provided in this embodiment includes: a main control CPU, a cell array, and a cell array bus. Different from the cell array in Embodiment 1, the cell array in this embodiment is a three-dimensional cell array (3D cell array) formed by superimposing more than one two-dimensional array, and the two-dimensional array is the cell array in Embodiment 1. A two-dimensional cell array (2D cell array) is also composed of more than one cell with computing and storage functions, each cell includes a microprocessor and a non-volatile random access memory, for details, refer to the relevant content described in Embodiment 1 .

[0177] In this embodiment, each cell stores its position in the c...

Embodiment 3

[0197] As mentioned above, the cells in the cell array in Embodiment 1 of the present invention have three functions of memory, storage and calculation, and the non-volatile random access memory in the cells can realize the data involved in the calculation of the microprocessor. random access, and can store software instruction codes and data that needs to be permanently stored, but the cost of the non-volatile random access memory is generally higher, so the non-volatile random access memory in the cell is used as the space of the memory part If the amount of data processed by the microprocessor in the cell is large, the limited memory space may affect the processing efficiency of the microprocessor. How to expand the memory space of the cell becomes an urgent problem to be solved.

[0198] Based on the above considerations, on the basis of the first embodiment, this embodiment provides another structure of the cell array computing system, such as Figure 15 As shown, in addi...

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Abstract

The invention discloses a cell array calculation system, comprising a CPU, a cell array, a cell array bus and a memory unit array; the cell array is a three-dimension cell array obtained through stacking more than one two-dimension cell array; the two-dimension cell array consists of more than one cell having functions of calculation and storage; at least one two-dimension cell array stacks with one or more than one corresponding memory unit arrays to form a three-dimension structure; the memory units in each memory unit are connected to the cells of the corresponding two-dimension cell array in one-to-one correspondence; each cell stores the position of itself in the cell array as an ID for the software or the hardware in the cell to read; a main control CPU performs communication with each cell in the cell array through the cell array bus; a communication interface is arranged between the adjacent cells in the cell array for transmitting data. The invention can overcome the communication bottleneck between the CPU and the memory and storage in the current computer architecture and improves the integral performance of the system.

Description

technical field [0001] The invention relates to the technical field of computers and computer applications, in particular to a cell array computing system. Background technique [0002] Generally speaking, a computer mainly includes three core parts: a central processing unit (CPU, Central Processing Unit), memory and storage. [0003] Through the unremitting efforts of some of the world's top companies, the CPU has evolved into an extremely complex semiconductor chip. The number of MOS tubes inside the top CPU core can exceed 100 million. The current industry trend is that it is difficult to increase the operating frequency of the CPU due to power consumption constraints. It is also difficult to improve the operating efficiency of the already extremely complex modern CPU. New CPU products are increasingly evolving towards multi-core. [0004] In terms of memory, the current dominant technology is Dynamic Random Access Memory (DRAM, Dynamic Random Access Memory) technolo...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06N3/00G06F15/163
Inventor 戴瑾郭一民王践识
Owner SHANGHAI CIYU INFORMATION TECH CO LTD
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