Buffer serial circuit based on transient voltage suppression

Abstract

The invention discloses a buffer serial circuit based on transient voltage suppression; the invention relates to the field of signal conversion and aims to solve the technical problems that the existing serializer exists mismatching of clock frequencies collected by different clock generators in the serializer, leads to relatively large output data error and simultaneously has switching loss and the like. The structure mainly comprises a first clock generator, a first multiplexing circuit, a feedback clock generator, a second multiplexing circuit and a reset circuit, wherein the first clock generator outputs a first clock signal and is used for constructing a signal collecting time window; a sampling clock port of the first multiplexing circuit receives the first clock signal output by the first clock generator, the input end receives a parallel source signal, and the output end outputs a mixed signal; and the reset circuit comprises a passive buffer circuit. The buffer serial circuit disclosed by the invention is used for high-speed serialization of the signal.

Description

technical field [0001] The invention relates to the field of signal conversion, in particular to a buffer serial circuit based on instantaneous voltage suppression. Background technique [0002] A serializer takes parallel data and converts it to a serial bit stream; the input signal is typically 8-bit parallel data, and usually uses some encoding scheme to convert the 8-bit data to 10-bit when transmitted on the serial output link data. Deserializers are the opposite process. It receives serial data, decodes it if necessary, and converts it to parallel formatted data. The deserializer also recovers the data clock and forwards the clock along with the data to subsequent components. These two complementary components in SerDes provide an efficient way to convert raw parallel data into serial data for efficient transmission; there is also a phase-locked loop (PLL) module in SerDes, which receives the system reference clock, and Multiplies it to the corresponding data rate....

AI Technical Summary

Problems solved by technology

[0005] In view of the above-mentioned prior art, the purpose of the present invention is to provide a buffer serial circuit based on instantaneous voltage suppression, which aims to solve the problem of unreasonable selection of the original data window area by the acquisition clock in the existing serializer. The acquisition clock frequency of different clock generators does not match, resulting in large output data errors. At the same time, there are technical problems such as slow data serial speed, limited operating efficiency, and switching loss.

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