Multi-core processor architecture based on MapReduce programming model
A technology of multi-core processors and programming models, applied in the fields of electrical digital data processing, instruments, computers, etc., which can solve the problems of slow processing speed and achieve the effect of increasing speed, more flexibility, and improving throughput
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[0037]The present invention will be further described below with reference to the accompanying drawings and in conjunction with specific application programs.
[0038] see figure 1 The invention discloses a multi-core processor architecture based on a MapReduce programming model, which connects processor clusters through a layered interconnection structure. Such as figure 1 As shown, the processor is mainly composed of three parts: the Split module divides the input data and assigns tasks; the MapReduce Block Pipeline (MapReduce Block-Pipe, referred to as MRBP) module composed of multiple block pipelines processes the divided data blocks into the data pair defined by the MapReduce programming model, where key represents the key value, and value represents the number of the key value; the back-end Merge module merges the results of the data pair output by the MRBP module, and All data pairs with the same key value are combined into a data pair.
[0039] Specifically, the ...
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