Chip packaging method and chip packaging structure

Abstract

The invention provides a chip packaging method and a chip packaging structure. The chip packaging method comprises the steps of forming a bonding wire pin on a first region of a carrier surface; forming an insulating layer on a non-active surface of a chip; adhering the chip to a second region of the carrier surface through the insulating layer; and after lead bonding and packaging process are completed, peeling off the carrier from a plastic packaging body to enable the insulating layer and the bonding wire pin to be exposed on the surface of the plastic packaging body. When the packaging structure formed by the packaging method is mounted on a PCB, the insulation between the non-active surface of the chip and the PCB can be ensured, and the electrical characteristic of the packaging structure is ensured as well; and in addition, according to the packaging method, a pre-fabricated lead frame is not required, instead, the bonding wire pin is formed in the packaging process, so that the flexibility of the packaging design can be improved.

Description

technical field [0001] The invention relates to the technical field of chip packaging, in particular to a chip packaging method and a chip packaging structure. Background technique [0002] The early chip package was a dual in-line DI package, which is more convenient for wiring and operation. However, the packaging efficiency of the DIP package is very low, and the area of ​​the packaged product is large, which is not conducive to increasing the capacity of the memory stick, and also affects the improvement of memory frequency, transmission rate and electrical performance. [0003] In order to reduce the packaging area of ​​the chip, surface mount technology (SMT packaging) has become a relatively popular packaging technology in the electronic assembly industry, and in SMT packaging, QFN packaging (quad flat no-lead packaging) has become the mainstream. The existing QFN packaging method is usually to install the non-active surface of the semiconductor bare chip on the midd...

AI Technical Summary

Problems solved by technology

[0004] However, some low-power devices do not have high requirements for heat dissipation performance, but they have very high requirements for the direct insulation between their non-active surface and PCB board, so as to prevent leakage and affect the performance of the chip.

For the packaging of this type of chip, the conventional QFN packaging method is no longer suitable.

In addition, in this conventional QFN package, it is necessary to use a prefabricated lead frame, and once the lead frame is made, the arrangement, spacing and size of the pins have been determined, which is not conducive to the flexible design of the package.

Images