Fault Tolerant Structure and Method of Cache in High Reliable System Chip

Abstract

The invention provides a fault-tolerant structure and a fault-tolerant method for a Cache in a high-reliability system chip, which can ensure a processor to keep relatively high performance. The method comprises: when a main control processor in a system chip accesses to a Cache memory and requests for a required instruction or required data, performing odd-even check decoding on information in the Cache memory in a cross grouping form, so that fault tolerance of the Cache memory is realized; if a check error is discovered, directly processing a current access as missing, performing an update operation on the Cache, re-writing correct data to the Cache memory according to an LRU policy, and performing odd-even check encoding in a cross grouping form on the written data, so that fault tolerance of the Cache memory is realized; and if the check error is not discovered, indicating that the information in the Cache memory is correct, and performing a hitting judgment operation according to the indication. With the adoption of a fault-tolerant policy for only checking and not correcting errors, the complexity of system design is greatly lowered, the logic delay of system design is greatly shortened, and greater influence of the Cache in a key path of the processor on a main frequency of the processor after the addition of the fault-tolerant structure is avoided.

Description

technical field [0001] The invention relates to the fault-tolerant design of the Cache in the highly reliable system chip, in particular to the fault-tolerant structure and the fault-tolerant method of the Cache in the highly reliable system chip. Background technique [0002] With the continuous improvement of the integrated circuit manufacturing process, the system chip (SoC) becomes more and more complex, and its functions become more and more powerful. However, in applications targeting space ionization environments, non-physical transient faults (soft errors) caused by factors such as particle radiation and noise interference have become increasingly prominent, and have gradually become the main reason for the failure of space application chips. In the system chip, Cache is used as the high-speed cache for the main control processor to access instructions and data, occupying most of the memory resources on the chip. While providing high performance, it also brings great...

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Problems solved by technology

Although this method can completely avoid the problem of chip failure caused by Cache errors, it fundamentally negates the significance of the existence of Cache and greatly reduces the execution performance of the processor. This is not an effective fault-tolerant means, usually will not use

[0006] It can be seen that when implementing a highly reliable system chip, the fault-tolerant technology for Cache either consumes too many hardware resources, or the design is too difficult, or seriously affects the execution performance of the processor.

How to implement Cache fault tolerance simply and effectively, and achieve a balance in reliability, auxiliary overhead, and performance has become an important problem for system chip designers to solve. After searching relevant literature and patents, no solution has been found. method of the problem

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